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Merge tag 'drm-misc-next-2020-06-26' of git://anongit.freedesktop.org/drm/drm-misc into drm-next
drm-misc-next for v5.9: Cross-subsystem Changes: - Improve dma-buf docs. Core Changes: - Add NV15, Q410, Q401 yuv formats. - Add uncompressed AFBC modifier. - Add DP helepr for reading Ignore MSA from DPCD. - Add missing panel type for some panels - Optimize drm/mm hole handling. - Constify connector to infoframe functions. - Add debugfs for VRR monitor range. Driver Changes: - Assorted small bugfixes in panfrost, malidp, panel/otm8009a. - Convert tfp410 dt bindings to yaml, and rework time calculations. - Add support for a few more simple panels. - Cleanups and optimizations for ast. - Allow adv7511 and simple-bridge to be used without connector creation. - Cleanups to dw-hdmi function prototypes. - Remove enabled bool from tiny/repaper and mipi-dbi, atomic handles it. - Remove unused header file from dw-mipi-dsi - Begin removing ttm_bo->offset. Signed-off-by: Dave Airlie <[email protected]> From: Maarten Lankhorst <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
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‎Documentation/devicetree/bindings/display/bridge/ti,tfp410.txt

Lines changed: 0 additions & 66 deletions
This file was deleted.

‎Documentation/devicetree/bindings/display/bridge/ti,tfp410.yaml

Lines changed: 131 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,131 @@
1+
# SPDX-License-Identifier: GPL-2.0-only
2+
%YAML 1.2
3+
---
4+
$id: http://devicetree.org/schemas/display/bridge/ti,tfp410.yaml#
5+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+
title: TFP410 DPI to DVI encoder
8+
9+
maintainers:
10+
- Tomi Valkeinen <[email protected]>
11+
- Jyri Sarha <[email protected]>
12+
13+
properties:
14+
compatible:
15+
const: ti,tfp410
16+
17+
reg:
18+
description: I2C address of the device.
19+
maxItems: 1
20+
21+
powerdown-gpios:
22+
maxItems: 1
23+
24+
ti,deskew:
25+
description:
26+
Data de-skew value in 350ps increments, from 0 to 7, as configured
27+
through the DK[3:1] pins. The de-skew multiplier is computed as
28+
(DK[3:1] - 4), so it ranges from -4 to 3.
29+
$ref: /schemas/types.yaml#/definitions/uint32
30+
minimum: 0
31+
maximum: 7
32+
33+
ports:
34+
description:
35+
A node containing input and output port nodes with endpoint
36+
definitions as documented in
37+
Documentation/devicetree/bindings/media/video-interfaces.txt
38+
type: object
39+
40+
properties:
41+
port@0:
42+
description: DPI input port.
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type: object
44+
45+
properties:
46+
reg:
47+
const: 0
48+
49+
endpoint:
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type: object
51+
52+
properties:
53+
pclk-sample:
54+
description:
55+
Endpoint sampling edge.
56+
enum:
57+
- 0 # Falling edge
58+
- 1 # Rising edge
59+
default: 0
60+
61+
bus-width:
62+
description:
63+
Endpoint bus width.
64+
enum:
65+
- 12 # 12 data lines connected and dual-edge mode
66+
- 24 # 24 data lines connected and single-edge mode
67+
default: 24
68+
69+
port@1:
70+
description: DVI output port.
71+
type: object
72+
73+
properties:
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reg:
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const: 1
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77+
endpoint:
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type: object
79+
80+
required:
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- port@0
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- port@1
83+
84+
required:
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- compatible
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- ports
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if:
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required:
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- reg
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then:
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properties:
93+
ti,deskew: false
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else:
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required:
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- ti,deskew
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98+
additionalProperties: false
99+
100+
examples:
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- |
102+
#include <dt-bindings/gpio/gpio.h>
103+
104+
tfp410: encoder {
105+
compatible = "ti,tfp410";
106+
powerdown-gpios = <&twl_gpio 2 GPIO_ACTIVE_LOW>;
107+
ti,deskew = <3>;
108+
109+
ports {
110+
#address-cells = <1>;
111+
#size-cells = <0>;
112+
113+
port@0 {
114+
reg = <0>;
115+
tfp410_in: endpoint {
116+
pclk-sample = <1>;
117+
bus-width = <24>;
118+
remote-endpoint = <&dpi_out>;
119+
};
120+
};
121+
122+
port@1 {
123+
reg = <1>;
124+
tfp410_out: endpoint {
125+
remote-endpoint = <&dvi_connector_in>;
126+
};
127+
};
128+
};
129+
};
130+
131+
...

‎Documentation/devicetree/bindings/display/panel/panel-simple.yaml

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Original file line numberDiff line numberDiff line change
@@ -81,6 +81,10 @@ properties:
8181
- boe,nv140fhmn49
8282
# CDTech(H.K.) Electronics Limited 4.3" 480x272 color TFT-LCD panel
8383
- cdtech,s043wq26h-ct7
84+
# CDTech(H.K.) Electronics Limited 7" WSVGA (1024x600) TFT LCD Panel
85+
- cdtech,s070pws19hp-fc21
86+
# CDTech(H.K.) Electronics Limited 7" WVGA (800x480) TFT LCD Panel
87+
- cdtech,s070swv29hg-dc44
8488
# CDTech(H.K.) Electronics Limited 7" 800x480 color TFT-LCD panel
8589
- cdtech,s070wv95-ct16
8690
# Chunghwa Picture Tubes Ltd. 7" WXGA TFT LCD panel
@@ -247,6 +251,8 @@ properties:
247251
- starry,kr122ea0sra
248252
# Tianma Micro-electronics TM070JDHG30 7.0" WXGA TFT LCD panel
249253
- tianma,tm070jdhg30
254+
# Tianma Micro-electronics TM070JVHG33 7.0" WXGA TFT LCD panel
255+
- tianma,tm070jvhg33
250256
# Tianma Micro-electronics TM070RVHG71 7.0" WXGA TFT LCD panel
251257
- tianma,tm070rvhg71
252258
# Toshiba 8.9" WXGA (1280x768) TFT LCD panel

‎Documentation/driver-api/dma-buf.rst

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Original file line numberDiff line numberDiff line change
@@ -100,11 +100,11 @@ CPU Access to DMA Buffer Objects
100100
.. kernel-doc:: drivers/dma-buf/dma-buf.c
101101
:doc: cpu access
102102

103-
Fence Poll Support
104-
~~~~~~~~~~~~~~~~~~
103+
Implicit Fence Poll Support
104+
~~~~~~~~~~~~~~~~~~~~~~~~~~~
105105

106106
.. kernel-doc:: drivers/dma-buf/dma-buf.c
107-
:doc: fence polling
107+
:doc: implicit fence polling
108108

109109
Kernel Functions and Structures Reference
110110
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

‎drivers/dma-buf/dma-buf.c

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Original file line numberDiff line numberDiff line change
@@ -161,11 +161,11 @@ static loff_t dma_buf_llseek(struct file *file, loff_t offset, int whence)
161161
}
162162

163163
/**
164-
* DOC: fence polling
164+
* DOC: implicit fence polling
165165
*
166166
* To support cross-device and cross-driver synchronization of buffer access
167-
* implicit fences (represented internally in the kernel with &struct fence) can
168-
* be attached to a &dma_buf. The glue for that and a few related things are
167+
* implicit fences (represented internally in the kernel with &struct dma_fence)
168+
* can be attached to a &dma_buf. The glue for that and a few related things are
169169
* provided in the &dma_resv structure.
170170
*
171171
* Userspace can query the state of these implicitly tracked fences using poll()

‎drivers/gpu/drm/amd/amdgpu/amdgpu_object.c

Lines changed: 21 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -918,7 +918,8 @@ int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain,
918918
bo->pin_count++;
919919

920920
if (max_offset != 0) {
921-
u64 domain_start = bo->tbo.bdev->man[mem_type].gpu_offset;
921+
u64 domain_start = amdgpu_ttm_domain_start(adev,
922+
mem_type);
922923
WARN_ON_ONCE(max_offset <
923924
(amdgpu_bo_gpu_offset(bo) - domain_start));
924925
}
@@ -1484,7 +1485,25 @@ u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo)
14841485
WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_VRAM &&
14851486
!(bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS));
14861487

1487-
return amdgpu_gmc_sign_extend(bo->tbo.offset);
1488+
return amdgpu_bo_gpu_offset_no_check(bo);
1489+
}
1490+
1491+
/**
1492+
* amdgpu_bo_gpu_offset_no_check - return GPU offset of bo
1493+
* @bo: amdgpu object for which we query the offset
1494+
*
1495+
* Returns:
1496+
* current GPU offset of the object without raising warnings.
1497+
*/
1498+
u64 amdgpu_bo_gpu_offset_no_check(struct amdgpu_bo *bo)
1499+
{
1500+
struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
1501+
uint64_t offset;
1502+
1503+
offset = (bo->tbo.mem.start << PAGE_SHIFT) +
1504+
amdgpu_ttm_domain_start(adev, bo->tbo.mem.mem_type);
1505+
1506+
return amdgpu_gmc_sign_extend(offset);
14881507
}
14891508

14901509
/**

‎drivers/gpu/drm/amd/amdgpu/amdgpu_object.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -293,6 +293,7 @@ int amdgpu_bo_sync_wait_resv(struct amdgpu_device *adev, struct dma_resv *resv,
293293
bool intr);
294294
int amdgpu_bo_sync_wait(struct amdgpu_bo *bo, void *owner, bool intr);
295295
u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo);
296+
u64 amdgpu_bo_gpu_offset_no_check(struct amdgpu_bo *bo);
296297
int amdgpu_bo_validate(struct amdgpu_bo *bo);
297298
int amdgpu_bo_restore_shadow(struct amdgpu_bo *shadow,
298299
struct dma_fence **fence);

‎drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c

Lines changed: 23 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -91,15 +91,13 @@ static int amdgpu_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
9191
case TTM_PL_TT:
9292
/* GTT memory */
9393
man->func = &amdgpu_gtt_mgr_func;
94-
man->gpu_offset = adev->gmc.gart_start;
9594
man->available_caching = TTM_PL_MASK_CACHING;
9695
man->default_caching = TTM_PL_FLAG_CACHED;
9796
man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA;
9897
break;
9998
case TTM_PL_VRAM:
10099
/* "On-card" video ram */
101100
man->func = &amdgpu_vram_mgr_func;
102-
man->gpu_offset = adev->gmc.vram_start;
103101
man->flags = TTM_MEMTYPE_FLAG_FIXED |
104102
TTM_MEMTYPE_FLAG_MAPPABLE;
105103
man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC;
@@ -110,7 +108,6 @@ static int amdgpu_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
110108
case AMDGPU_PL_OA:
111109
/* On-chip GDS memory*/
112110
man->func = &ttm_bo_manager_func;
113-
man->gpu_offset = 0;
114111
man->flags = TTM_MEMTYPE_FLAG_FIXED | TTM_MEMTYPE_FLAG_CMA;
115112
man->available_caching = TTM_PL_FLAG_UNCACHED;
116113
man->default_caching = TTM_PL_FLAG_UNCACHED;
@@ -258,7 +255,8 @@ static uint64_t amdgpu_mm_node_addr(struct ttm_buffer_object *bo,
258255

259256
if (mm_node->start != AMDGPU_BO_INVALID_OFFSET) {
260257
addr = mm_node->start << PAGE_SHIFT;
261-
addr += bo->bdev->man[mem->mem_type].gpu_offset;
258+
addr += amdgpu_ttm_domain_start(amdgpu_ttm_adev(bo->bdev),
259+
mem->mem_type);
262260
}
263261
return addr;
264262
}
@@ -843,6 +841,27 @@ static unsigned long amdgpu_ttm_io_mem_pfn(struct ttm_buffer_object *bo,
843841
(offset >> PAGE_SHIFT);
844842
}
845843

844+
/**
845+
* amdgpu_ttm_domain_start - Returns GPU start address
846+
* @adev: amdgpu device object
847+
* @type: type of the memory
848+
*
849+
* Returns:
850+
* GPU start address of a memory domain
851+
*/
852+
853+
uint64_t amdgpu_ttm_domain_start(struct amdgpu_device *adev, uint32_t type)
854+
{
855+
switch (type) {
856+
case TTM_PL_TT:
857+
return adev->gmc.gart_start;
858+
case TTM_PL_VRAM:
859+
return adev->gmc.vram_start;
860+
}
861+
862+
return 0;
863+
}
864+
846865
/*
847866
* TTM backend functions.
848867
*/
@@ -1239,9 +1258,6 @@ int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo)
12391258
bo->mem = tmp;
12401259
}
12411260

1242-
bo->offset = (bo->mem.start << PAGE_SHIFT) +
1243-
bo->bdev->man[bo->mem.mem_type].gpu_offset;
1244-
12451261
return 0;
12461262
}
12471263

‎drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -112,6 +112,7 @@ int amdgpu_fill_buffer(struct amdgpu_bo *bo,
112112
int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma);
113113
int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo);
114114
int amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo);
115+
uint64_t amdgpu_ttm_domain_start(struct amdgpu_device *adev, uint32_t type);
115116

116117
#if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR)
117118
int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages);

‎drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -144,7 +144,7 @@ static void amdgpu_vm_sdma_copy_ptes(struct amdgpu_vm_update_params *p,
144144

145145
src += p->num_dw_left * 4;
146146

147-
pe += amdgpu_gmc_sign_extend(bo->tbo.offset);
147+
pe += amdgpu_bo_gpu_offset_no_check(bo);
148148
trace_amdgpu_vm_copy_ptes(pe, src, count, p->immediate);
149149

150150
amdgpu_vm_copy_pte(p->adev, ib, pe, src, count);
@@ -171,7 +171,7 @@ static void amdgpu_vm_sdma_set_ptes(struct amdgpu_vm_update_params *p,
171171
{
172172
struct amdgpu_ib *ib = p->job->ibs;
173173

174-
pe += amdgpu_gmc_sign_extend(bo->tbo.offset);
174+
pe += amdgpu_bo_gpu_offset_no_check(bo);
175175
trace_amdgpu_vm_set_ptes(pe, addr, count, incr, flags, p->immediate);
176176
if (count < 3) {
177177
amdgpu_vm_write_pte(p->adev, ib, pe, addr | flags,

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