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lumag
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phy: qualcomm: qmp-pcie: split PCS_LANE1 region
The PCS_LANE1 region isn't a part of the PCS_PCIE region. It was handled this way as it simplified handled of devices with the old bindings. Nowadays it can be handled as is, without hacks. Split the PCS_LANE1 region from the PCS_PCIE / PCS_MISC region space. Signed-off-by: Dmitry Baryshkov <[email protected]> Reviewed-by: Neil Armstrong <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
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-9
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3 files changed

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-9
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‎drivers/phy/qualcomm/phy-qcom-qmp-pcie.c‎

Lines changed: 27 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1850,7 +1850,7 @@ static const struct qmp_phy_init_tbl sdx55_qmp_pcie_rc_pcs_misc_tbl[] = {
18501850
QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
18511851
};
18521852

1853-
static const struct qmp_phy_init_tbl sdx55_qmp_pcie_ep_pcs_misc_tbl[] = {
1853+
static const struct qmp_phy_init_tbl sdx55_qmp_pcie_ep_pcs_lane1_tbl[] = {
18541854
QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2, 0x00),
18551855
QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00),
18561856
};
@@ -1984,6 +1984,9 @@ static const struct qmp_phy_init_tbl sdx65_qmp_pcie_pcs_misc_tbl[] = {
19841984
QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG2, 0x0d),
19851985
QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02),
19861986
QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN, 0x2e),
1987+
};
1988+
1989+
static const struct qmp_phy_init_tbl sdx65_qmp_pcie_pcs_lane1_tbl[] = {
19871990
QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_LANE1_INSIG_SW_CTRL2, 0x00),
19881991
QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00),
19891992
};
@@ -2659,8 +2662,6 @@ static const struct qmp_phy_init_tbl sa8775p_qmp_gen4_pcie_rc_pcs_misc_tbl[] = {
26592662
static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x2_pcie_pcs_alt_tbl[] = {
26602663
QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG4, 0x16),
26612664
QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG5, 0x22),
2662-
QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_LANE1_INSIG_SW_CTRL2, 0x00),
2663-
QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00),
26642665
QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_G3S2_PRE_GAIN, 0x2e),
26652666
QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_RX_SIGDET_LVL, 0x66),
26662667
};
@@ -2805,6 +2806,7 @@ struct qmp_pcie_offsets {
28052806
u16 serdes;
28062807
u16 pcs;
28072808
u16 pcs_misc;
2809+
u16 pcs_lane1;
28082810
u16 tx;
28092811
u16 rx;
28102812
u16 tx2;
@@ -2829,6 +2831,8 @@ struct qmp_phy_cfg_tbls {
28292831
int pcs_num;
28302832
const struct qmp_phy_init_tbl *pcs_misc;
28312833
int pcs_misc_num;
2834+
const struct qmp_phy_init_tbl *pcs_lane1;
2835+
int pcs_lane1_num;
28322836
const struct qmp_phy_init_tbl *ln_shrd;
28332837
int ln_shrd_num;
28342838
};
@@ -2888,6 +2892,7 @@ struct qmp_pcie {
28882892
void __iomem *serdes;
28892893
void __iomem *pcs;
28902894
void __iomem *pcs_misc;
2895+
void __iomem *pcs_lane1;
28912896
void __iomem *tx;
28922897
void __iomem *rx;
28932898
void __iomem *tx2;
@@ -3004,6 +3009,7 @@ static const struct qmp_pcie_offsets qmp_pcie_offsets_v4_20 = {
30043009
.serdes = 0x1000,
30053010
.pcs = 0x1200,
30063011
.pcs_misc = 0x1600,
3012+
.pcs_lane1 = 0x1e00,
30073013
.tx = 0x0000,
30083014
.rx = 0x0200,
30093015
.tx2 = 0x0800,
@@ -3034,6 +3040,7 @@ static const struct qmp_pcie_offsets qmp_pcie_offsets_v5_20 = {
30343040
.serdes = 0x1000,
30353041
.pcs = 0x1200,
30363042
.pcs_misc = 0x1400,
3043+
.pcs_lane1 = 0x1e00,
30373044
.tx = 0x0000,
30383045
.rx = 0x0200,
30393046
.tx2 = 0x0800,
@@ -3542,8 +3549,8 @@ static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = {
35423549
.tbls_ep = &(const struct qmp_phy_cfg_tbls) {
35433550
.serdes = sdx55_qmp_pcie_ep_serdes_tbl,
35443551
.serdes_num = ARRAY_SIZE(sdx55_qmp_pcie_ep_serdes_tbl),
3545-
.pcs_misc = sdx55_qmp_pcie_ep_pcs_misc_tbl,
3546-
.pcs_misc_num = ARRAY_SIZE(sdx55_qmp_pcie_ep_pcs_misc_tbl),
3552+
.pcs_lane1 = sdx55_qmp_pcie_ep_pcs_lane1_tbl,
3553+
.pcs_lane1_num = ARRAY_SIZE(sdx55_qmp_pcie_ep_pcs_lane1_tbl),
35473554
},
35483555

35493556
.reset_list = sdm845_pciephy_reset_l,
@@ -3642,6 +3649,8 @@ static const struct qmp_phy_cfg sdx65_qmp_pciephy_cfg = {
36423649
.pcs_num = ARRAY_SIZE(sdx65_qmp_pcie_pcs_tbl),
36433650
.pcs_misc = sdx65_qmp_pcie_pcs_misc_tbl,
36443651
.pcs_misc_num = ARRAY_SIZE(sdx65_qmp_pcie_pcs_misc_tbl),
3652+
.pcs_lane1 = sdx65_qmp_pcie_pcs_lane1_tbl,
3653+
.pcs_lane1_num = ARRAY_SIZE(sdx65_qmp_pcie_pcs_lane1_tbl),
36453654
},
36463655
.reset_list = sdm845_pciephy_reset_l,
36473656
.num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
@@ -3841,6 +3850,8 @@ static const struct qmp_phy_cfg sa8775p_qmp_gen4x2_pciephy_cfg = {
38413850
.pcs_num = ARRAY_SIZE(sa8775p_qmp_gen4x2_pcie_pcs_alt_tbl),
38423851
.pcs_misc = sa8775p_qmp_gen4_pcie_pcs_misc_tbl,
38433852
.pcs_misc_num = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_pcs_misc_tbl),
3853+
.pcs_lane1 = sdx65_qmp_pcie_pcs_lane1_tbl,
3854+
.pcs_lane1_num = ARRAY_SIZE(sdx65_qmp_pcie_pcs_lane1_tbl),
38443855
},
38453856

38463857
.tbls_rc = &(const struct qmp_phy_cfg_tbls) {
@@ -4047,6 +4058,7 @@ static void qmp_pcie_init_registers(struct qmp_pcie *qmp, const struct qmp_phy_c
40474058
void __iomem *rx2 = qmp->rx2;
40484059
void __iomem *pcs = qmp->pcs;
40494060
void __iomem *pcs_misc = qmp->pcs_misc;
4061+
void __iomem *pcs_lane1 = qmp->pcs_lane1;
40504062
void __iomem *ln_shrd = qmp->ln_shrd;
40514063

40524064
if (!tbls)
@@ -4071,6 +4083,7 @@ static void qmp_pcie_init_registers(struct qmp_pcie *qmp, const struct qmp_phy_c
40714083

40724084
qmp_configure(qmp->dev, pcs, tbls->pcs, tbls->pcs_num);
40734085
qmp_configure(qmp->dev, pcs_misc, tbls->pcs_misc, tbls->pcs_misc_num);
4086+
qmp_configure(qmp->dev, pcs_lane1, tbls->pcs_lane1, tbls->pcs_lane1_num);
40744087

40754088
if (cfg->lanes >= 4 && qmp->tcsr_4ln_config) {
40764089
qmp_configure(qmp->dev, serdes, cfg->serdes_4ln_tbl,
@@ -4522,6 +4535,14 @@ static int qmp_pcie_parse_dt_legacy(struct qmp_pcie *qmp, struct device_node *np
45224535
}
45234536
}
45244537

4538+
/*
4539+
* For all platforms where legacy bindings existed, PCS_LANE1 was
4540+
* mapped as a part of the PCS_MISC region.
4541+
*/
4542+
if (!IS_ERR(qmp->pcs_misc) && cfg->offsets->pcs_lane1 != 0)
4543+
qmp->pcs_lane1 = qmp->pcs_misc +
4544+
(cfg->offsets->pcs_lane1 - cfg->offsets->pcs_misc);
4545+
45254546
clk = devm_get_clk_from_child(dev, np, NULL);
45264547
if (IS_ERR(clk)) {
45274548
return dev_err_probe(dev, PTR_ERR(clk),
@@ -4589,6 +4610,7 @@ static int qmp_pcie_parse_dt(struct qmp_pcie *qmp)
45894610
qmp->serdes = base + offs->serdes;
45904611
qmp->pcs = base + offs->pcs;
45914612
qmp->pcs_misc = base + offs->pcs_misc;
4613+
qmp->pcs_lane1 = base + offs->pcs_lane1;
45924614
qmp->tx = base + offs->tx;
45934615
qmp->rx = base + offs->rx;
45944616

‎drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v4_20.h‎

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -13,7 +13,8 @@
1313
#define QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME 0x0f4
1414
#define QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2 0x0fc
1515
#define QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5 0x108
16-
#define QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2 0x824
17-
#define QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2 0x828
16+
17+
#define QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2 0x024
18+
#define QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2 0x028
1819

1920
#endif

‎drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5_20.h‎

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -17,7 +17,8 @@
1717
#define QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5 0x108
1818
#define QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN 0x15c
1919
#define QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3 0x184
20-
#define QPHY_V5_20_PCS_LANE1_INSIG_SW_CTRL2 0xa24
21-
#define QPHY_V5_20_PCS_LANE1_INSIG_MX_CTRL2 0xa28
20+
21+
#define QPHY_V5_20_PCS_LANE1_INSIG_SW_CTRL2 0x024
22+
#define QPHY_V5_20_PCS_LANE1_INSIG_MX_CTRL2 0x028
2223

2324
#endif

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