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Define CSR Address width #30

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Define CSR Address width #30

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19a97ac
CSR addr is only 12bits
howard0su Aug 31, 2019
1fe5e32
Add CSR related defines
howard0su Aug 31, 2019
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6 changes: 3 additions & 3 deletions rtl/e203/core/e203_core.v
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Expand Up @@ -33,10 +33,10 @@ module e203_core(
`ifdef E203_HAS_CSR_EAI//{
output eai_csr_valid,
input eai_csr_ready,
output [31:0] eai_csr_addr,
output [`E203_CSR_ADDR_W-1:0] eai_csr_addr,
output eai_csr_wr,
output [31:0] eai_csr_wdata,
input [31:0] eai_csr_rdata,
output [`E203_XLEN-1:0] eai_csr_wdata,
input [`E203_XLEN-1:0] eai_csr_rdata,
`endif//}
output core_wfi,
output tm_stop,
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6 changes: 3 additions & 3 deletions rtl/e203/core/e203_cpu.v
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Expand Up @@ -440,10 +440,10 @@ module e203_cpu #(
`ifdef E203_HAS_CSR_EAI//{
wire eai_csr_valid;
wire eai_csr_ready;
wire [31:0] eai_csr_addr;
wire [`E203_CSR_ADDR_W-1:0] eai_csr_addr;
wire eai_csr_wr;
wire [31:0] eai_csr_wdata;
wire [31:0] eai_csr_rdata;
wire [`E203_XLEN-1:0] eai_csr_wdata;
wire [`E203_XLEN-1:0] eai_csr_rdata;

// This is an empty module to just connect the EAI CSR interface,
// user can hack it to become a real one
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2 changes: 2 additions & 0 deletions rtl/e203/core/e203_defines.v
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Expand Up @@ -70,6 +70,8 @@

`define E203_INSTR_SIZE 32

`define E203_CSR_ADDR_W 12

//
`define E203_RFIDX_WIDTH 5
`ifdef E203_CFG_REGNUM_IS_32//{
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6 changes: 3 additions & 3 deletions rtl/e203/core/e203_extend_csr.v
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Expand Up @@ -35,10 +35,10 @@ module e203_extend_csr(
input eai_csr_valid,
output eai_csr_ready,

input [31:0] eai_csr_addr,
input [`E203_CSR_ADDR_W-1:0] eai_csr_addr,
input eai_csr_wr,
input [31:0] eai_csr_wdata,
output [31:0] eai_csr_rdata,
input [`E203_XLEN-1:0] eai_csr_wdata,
output [`E203_XLEN-1:0] eai_csr_rdata,

input clk,
input rst_n
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6 changes: 3 additions & 3 deletions rtl/e203/core/e203_exu.v
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Expand Up @@ -166,10 +166,10 @@ module e203_exu(
`ifdef E203_HAS_CSR_EAI//{
output eai_csr_valid,
input eai_csr_ready,
output [31:0] eai_csr_addr,
output [`E203_CSR_ADDR_W-1:0] eai_csr_addr,
output eai_csr_wr,
output [31:0] eai_csr_wdata,
input [31:0] eai_csr_rdata,
output [`E203_XLEN-1:0] eai_csr_wdata,
input [`E203_XLEN-1:0] eai_csr_rdata,
`endif//}


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6 changes: 3 additions & 3 deletions rtl/e203/core/e203_exu_alu.v
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Expand Up @@ -45,10 +45,10 @@ module e203_exu_alu(
`endif//
output eai_csr_valid,
input eai_csr_ready,
output [31:0] eai_csr_addr,
output [`E203_CSR_ADDR_W-1:0] eai_csr_addr,
output eai_csr_wr,
output [31:0] eai_csr_wdata,
input [31:0] eai_csr_rdata,
output [`E203_XLEN-1:0] eai_csr_wdata,
input [`E203_XLEN-1:0] eai_csr_rdata,
`endif//}

output amo_wait,
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6 changes: 3 additions & 3 deletions rtl/e203/core/e203_exu_alu_csrctrl.v
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Expand Up @@ -54,10 +54,10 @@ module e203_exu_alu_csrctrl(
input eai_xs_off,
output eai_csr_valid,
input eai_csr_ready,
output [31:0] eai_csr_addr,
output [`E203_CSR_ADDR_W-1:0] eai_csr_addr,
output eai_csr_wr,
output [31:0] eai_csr_wdata,
input [31:0] eai_csr_rdata,
output [`E203_XLEN-1:0] eai_csr_wdata,
input [`E203_XLEN-1:0] eai_csr_rdata,
`endif//}


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2 changes: 1 addition & 1 deletion rtl/e203/core/e203_exu_csr.v
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Expand Up @@ -33,7 +33,7 @@ module e203_exu_csr(
input csr_ena,
input csr_wr_en,
input csr_rd_en,
input [12-1:0] csr_idx,
input [`E203_CSR_ADDR_W-1:0] csr_idx,

output csr_access_ilgl,
output tm_stop,
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