Name		Name	Last commit message	Last commit date
ALU.v		ALU.v
Branch.v		Branch.v
Data_RAM.v		Data_RAM.v
Decode.v		Decode.v
Execute.v		Execute.v
Fetch.v		Fetch.v
Loadstore.v		Loadstore.v
Processor.v		Processor.v
Processor_Compiled.v		Processor_Compiled.v
Prog_Count.v		Prog_Count.v
Prog_Mem.v		Prog_Mem.v
RAM.v		RAM.v
README.md		README.md

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RISCV-Processor-ASIC

Author: Soham Kapur
Description: This is a basic RISC-V based processor under development. It follows the 32-bit Integer ISA.

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This is a basic RISC-V based processor under development. It follows the 32-bit Integer ISA.

asic asic-design asic-verification fpga hardware-designs open-source openlane openlane-flow processor-architecture processor-design risc-v riscv32 verilog verilog-hdl vlsi vlsi-design

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