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TEST HELLO WORLD

Analog-Design-of-LDO-with-PMOS-pass-device

This project discusses the design procedure of a conventional Low Dropout Voltage Regulator (LDO) circuit. The circuit consists of 2 stages, a 5-transistor operational transconductance amplifier (OTA) & a pass transistor. The circuit produces a regulated voltage of 0.9V using a reference voltage of 0.75V & a supply of 1.2V.

LDO Circuit Diagram

LDO with RC compensation

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Simulations

a) Monte Carlo - Offset Variation:

b) AC & STB - PSRR, PM, & Noise:

c) Noise:

d) Step-Load (Transient) VS AC/STB Sweep:

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Results Summary

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Key References:

[1] P. K. Hanumolu, "Low dropout regulators," 2015 IEEE Custom Integrated Circuits Conference (CICC), San Jose, CA, USA, 2015, pp. 1-37, doi: 10.1109/CICC.2015.7338435.

[2] T. Carusone, D. Jones, K. Martin, "Analog Integrated Circuit Design", 2nd Ed., Ch.7: Biasing, References & Regulators, John Wiley & Sons, Inc, 2012.

[3] B. Razavi, "The Low Dropout Regulator [A Circuit for All Seasons]," in IEEE Solid-State Circuits Magazine, vol. 11, no. 2, pp. 8-13, Spring 2019, doi: 10.1109/MSSC.2019.2910952.

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Project Links:

1. Report: Project_Report_LDO.pdf
2. Testbench Details: Testbenches_&_Results.pptx
3. Hand Analysis: ldo_hand_analysis.pdf
   
   >> Drive: https://drive.google.com/drive/folders/1lhqr3ftbG6R5mv5Qr27eAjxs_dBoFz7P?usp=drive_link