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95dca6f
fix when STR LDR V0 Register this immediate must << 4 ins : E0 0B 8…
IIIImmmyyy Apr 30, 2025
d9591ef
fix movz when shift is not zero and this result is int64 , it can cha…
IIIImmmyyy May 8, 2025
336dab3
fix FCVT
IIIImmmyyy May 15, 2025
63356b9
fix E8 07 45 FC LDR D8, [SP+0x50+var_5…
IIIImmmyyy May 29, 2025
3488c81
rollback
IIIImmmyyy May 29, 2025
b6a4431
bug fix
IIIImmmyyy May 29, 2025
093ccea
fix D0 parser v0
IIIImmmyyy Jun 3, 2025
723623d
fix MOVK!
IIIImmmyyy Jun 9, 2025
6f852a1
support fcvt
IIIImmmyyy Jun 13, 2025
d875ce3
fix s0 parser error to v0
IIIImmmyyy Jun 13, 2025
6df0faa
support more ins
IIIImmmyyy Jun 14, 2025
72a9e18
修复指令
IIIImmmyyy Jun 14, 2025
7d82bda
fix SIMD DUP ins
IIIImmmyyy Jun 14, 2025
cd0877f
fix REV64
IIIImmmyyy Jun 14, 2025
742ea72
1
IIIImmmyyy Jun 14, 2025
1c2721a
bug fix
IIIImmmyyy Jun 16, 2025
0692f00
support more aliases
IIIImmmyyy Jun 17, 2025
8c6e5ec
bug fix
IIIImmmyyy Jun 18, 2025
a98e4dd
fix FMOV with immdata
IIIImmmyyy Jun 18, 2025
23c398f
UDP INS is better
IIIImmmyyy Jun 19, 2025
2162858
support more alia
IIIImmmyyy Jun 24, 2025
3d6961c
add BFM to BFI alias conversion
IIIImmmyyy Jul 16, 2025
8cc4324
enhance BFM to BFXIL and BFI conversion logic
IIIImmmyyy Jul 21, 2025
d18c557
refactor SMADDL instruction handling for optimized operand management
IIIImmmyyy Jul 22, 2025
c756c21
refactor SMADDL and UMADDL instruction handling for proper aliasing t…
IIIImmmyyy Jul 23, 2025
9dbe694
refactor variable shift instruction handling for improved alias reada…
IIIImmmyyy Jul 23, 2025
598dae6
update EXT Ins
IIIImmmyyy Jul 23, 2025
5cbdb5b
refactor Arm64Branches to improve bit testing logic and register sele…
IIIImmmyyy Sep 11, 2025
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16 changes: 9 additions & 7 deletions Disarm/Arm64Instruction.cs
Original file line number Diff line number Diff line change
Expand Up @@ -147,13 +147,13 @@ public override string ToString()
sb.Append(' ');

//Ew yes I'm using goto.
if (!AppendOperand(sb, Op0Kind, Op0Reg, Op0VectorElement, Op0Arrangement, Op1ShiftType, Op0Imm, Op0FpImm))
if (!AppendOperand(sb, Op0Kind, Op0Reg, Op0VectorElement, Op0Arrangement, Op0ShiftType, Op0Imm, Op0FpImm, false, MemExtendOrShiftAmount))
goto doneops;
if (!AppendOperand(sb, Op1Kind, Op1Reg, Op1VectorElement, Op1Arrangement, Op1ShiftType, Op1Imm, Op1FpImm, true))
if (!AppendOperand(sb, Op1Kind, Op1Reg, Op1VectorElement, Op1Arrangement, Op1ShiftType, Op1Imm, Op1FpImm, true, MemExtendOrShiftAmount))
goto doneops;
if (!AppendOperand(sb, Op2Kind, Op2Reg, Op2VectorElement, Op2Arrangement, Op1ShiftType, Op2Imm, Op2FpImm, true))
if (!AppendOperand(sb, Op2Kind, Op2Reg, Op2VectorElement, Op2Arrangement, Op2ShiftType, Op2Imm, Op2FpImm, true, MemExtendOrShiftAmount))
goto doneops;
if (!AppendOperand(sb, Op3Kind, Op3Reg, Op3VectorElement, Op3Arrangement, Op1ShiftType, Op3Imm, Op3FpImm, true))
if (!AppendOperand(sb, Op3Kind, Op3Reg, Op3VectorElement, Op3Arrangement, Op3ShiftType, Op3Imm, Op3FpImm, true, MemExtendOrShiftAmount))
goto doneops;

doneops:
Expand All @@ -167,7 +167,7 @@ public override string ToString()
return sb.ToString();
}

private bool AppendOperand(StringBuilder sb, Arm64OperandKind kind, Arm64Register reg, Arm64VectorElement vectorElement, Arm64ArrangementSpecifier regArrangement, Arm64ShiftType shiftType, long imm, double fpImm, bool comma = false)
private bool AppendOperand(StringBuilder sb, Arm64OperandKind kind, Arm64Register reg, Arm64VectorElement vectorElement, Arm64ArrangementSpecifier regArrangement, Arm64ShiftType shiftType, long imm, double fpImm, bool comma = false, int shiftAmount = 0)
{
if (kind == Arm64OperandKind.None)
return false;
Expand All @@ -189,12 +189,14 @@ private bool AppendOperand(StringBuilder sb, Arm64OperandKind kind, Arm64Registe
}
else if (kind == Arm64OperandKind.Immediate)
{
sb.Append("#0x").Append(imm.ToString("X"));
if (shiftType != Arm64ShiftType.NONE)
sb.Append(shiftType).Append(' ');
sb.Append("0x").Append(imm.ToString("X"));
sb.Append(",").Append(shiftType).Append("#").Append(shiftAmount);
} else if (kind == Arm64OperandKind.FloatingPointImmediate)
{
sb.Append("#");
sb.Append(fpImm.ToString(CultureInfo.InvariantCulture));

}
else if(kind == Arm64OperandKind.ImmediatePcRelative)
sb.Append("0x").Append(((long) Address + imm).ToString("X"));
Expand Down
9 changes: 9 additions & 0 deletions Disarm/Arm64Mnemonic.cs
Original file line number Diff line number Diff line change
Expand Up @@ -102,6 +102,7 @@ public enum Arm64Mnemonic
CLREX,
CLS,
CLZ,
CNT,
CMN,
CMP,
CMPP,
Expand Down Expand Up @@ -139,6 +140,7 @@ public enum Arm64Mnemonic
ERETAB,
ESB,
EXTR,
EXT, // Advanced SIMD extract
FABD,
FABS,
FACGE,
Expand Down Expand Up @@ -552,6 +554,8 @@ public enum Arm64Mnemonic
TLBI,
TSB_CSYNC,
TST,
TRN1,
TRN2,
RSUBHN, RSUBHN2,
SABA,
SABAL, SABAL2,
Expand Down Expand Up @@ -712,13 +716,18 @@ public enum Arm64Mnemonic
UMULL,
UXTB,
UXTH,
UZP1,
UZP2,
WFE,
WFET,
WFI,
WFIT,
XAFLAG,
XTN,
XPACD,XPACI,XPACLRI,
YIELD,
ZIP1,
ZIP2,
CMHL,
CMHS,
CMHI,
Expand Down
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