-> Designed an adder utilizing a Tree-Structure, leading to logarithmic time complexity for better efficiency.
-> Implemented AND, XOR, (A+B.C) logic to compute different order Generate and Propogate expressions.
-> Analyzed the structural description of each level of tree for generating final sum and carry output.
-> Implemented the design in VHDL using Quartus and verified with multiple test vectors in Modelsim.