Aspiring computer architect and rtl designer. Always looking to learn something new.
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32-bit-RiscV-CPU
32-bit-RiscV-CPU PublicA 32-bit RISC-V based CPU personal project. I am always making improvements as I grow and learn as an engineer.
Verilog
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buffets
buffets PublicForked from cwfletcher/buffets
Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.
Verilog
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