Merge pull request stm32-rs#238 from Sh3Rm4n/uart-refactor

Allow Serial::new instead of Serial::usartX

Author: Sh3Rm4n

CHANGELOG.md

@@ -19,6 +19,10 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 - `ld` feature, which enables the memory.x generation ([#216])
 - Implement `DelayMs` for `Milliseconds` and `DelayUs` for `Microseconds` ([#234])
 - ADC can now be `free()`'d ([#212])
+- Serial does now implement `embedded_hal::serial::{Read, Write}`.
+  No `split()` necessary. ([#232])
+- Serial can now listen for the "Transmission Complete" `Tc` interrupt event ([#232])
+- Serial can now listen for the `Idle` interrupt event ([#238])
 
 ### Changed
 
@@ -70,6 +74,7 @@ let clocks = rcc
 - Remove `stm32` module. Use `use stm32f3xx_hal::pac` instead.
   This module was a deprecated in [v0.5.0][] and is now subject for
   removal. ([#220])
+- `Serial::uart1` ... functions are renamed to `Serial::new`. ([#212])
 
 ## [v0.6.1] - 2020-12-10
 
@@ -325,6 +330,7 @@ let clocks = rcc
 [filter]: https://defmt.ferrous-systems.com/filtering.html
 
 [#234]: https://github.com/stm32-rs/stm32f3xx-hal/pull/234
+[#232]: https://github.com/stm32-rs/stm32f3xx-hal/pull/232
 [#229]: https://github.com/stm32-rs/stm32f3xx-hal/pull/229
 [#227]: https://github.com/stm32-rs/stm32f3xx-hal/pull/227
 [#220]: https://github.com/stm32-rs/stm32f3xx-hal/pull/220

examples/serial_dma.rs

@@ -29,7 +29,7 @@ fn main() -> ! {
             .pa10
             .into_af7_push_pull(&mut gpioa.moder, &mut gpioa.otyper, &mut gpioa.afrh),
     );
-    let serial = Serial::usart1(dp.USART1, pins, 9600.Bd(), clocks, &mut rcc.apb2);
+    let serial = Serial::new(dp.USART1, pins, 9600.Bd(), clocks, &mut rcc.apb2);
     let (tx, rx) = serial.split();
 
     let dma1 = dp.DMA1.split(&mut rcc.ahb);

examples/serial_echo_rtic.rs

@@ -64,13 +64,8 @@ mod app {
                 .into_af7_push_pull(&mut gpioa.moder, &mut gpioa.otyper, &mut gpioa.afrh),
         );
         pins.1.internal_pull_up(&mut gpioa.pupdr, true);
-        let mut serial: SerialType = Serial::usart1(
-            cx.device.USART1,
-            pins,
-            19200_u32.Bd(),
-            clocks,
-            &mut rcc.apb2,
-        );
+        let mut serial: SerialType =
+            Serial::new(cx.device.USART1, pins, 19200.Bd(), clocks, &mut rcc.apb2);
         serial.listen(Event::Rxne);
 
         rprintln!("post init");

src/dma.rs

@@ -333,7 +333,10 @@ pub trait Channel: private::Channel {
             1 => BITS8,
             2 => BITS16,
             4 => BITS32,
-            s => crate::panic!("unsupported word size: {:?}", s),
+            #[cfg(not(feature = "defmt"))]
+            s => core::panic!("unsupported word size: {:?}", s),
+            #[cfg(feature = "defmt")]
+            _ => defmt::panic!("unsupported word size"),
         };
 
         self.ch().cr.modify(|_, w| {

src/gpio.rs

@@ -275,6 +275,9 @@ pub struct Pin<Gpio, Index, Mode> {
     _mode: PhantomData<Mode>,
 }
 
+// Make all GPIO peripheral trait extensions sealable.
+impl<Gpio, Index, Mode> crate::private::Sealed for Pin<Gpio, Index, Mode> {}
+
 /// Fully erased pin
 ///
 /// This moves the pin type information to be known

src/i2c.rs

@@ -132,15 +132,15 @@ impl<I2C, SCL, SDA> I2c<I2C, (SCL, SDA)> {
         // t_SCL ~= t_SYNC1 + t_SYNC2 + t_SCLL + t_SCLH
         let i2cclk = I2C::clock(&clocks).0;
         let ratio = i2cclk / freq.integer() - 4;
-        let (presc, scll, sclh, sdadel, scldel) = if freq.integer() >= 100_000 {
+        let (presc, scll, sclh, sdadel, scldel) = if freq >= 100.kHz() {
             // fast-mode or fast-mode plus
             // here we pick SCLL + 1 = 2 * (SCLH + 1)
             let presc = ratio / 387;
 
             let sclh = ((ratio / (presc + 1)) - 3) / 3;
             let scll = 2 * (sclh + 1) - 1;
 
-            let (sdadel, scldel) = if freq.integer() > 400_000 {
+            let (sdadel, scldel) = if freq > 400.kHz() {
                 // fast-mode plus
                 let sdadel = 0;
                 let scldel = i2cclk / 4_000_000 / (presc + 1) - 1;
@@ -449,7 +449,7 @@ macro_rules! i2c {
                 fn clock(clocks: &Clocks) -> Hertz {
                     // NOTE(unsafe) atomic read with no side effects
                     match unsafe { (*RCC::ptr()).cfgr3.read().$i2cXsw().variant() } {
-                        I2C1SW_A::HSI => Hertz(8_000_000),
+                        I2C1SW_A::HSI => crate::rcc::HSI,
                         I2C1SW_A::SYSCLK => clocks.sysclk(),
                     }
                 }

src/lib.rs

@@ -161,7 +161,9 @@ pub mod watchdog;
 
 cfg_if! {
     if #[cfg(feature = "defmt")] {
+        #[allow(unused_imports)]
         pub(crate) use defmt::{assert, panic, unreachable, unwrap};
+        #[allow(unused_imports)]
         pub(crate) use macros::expect;
 
         mod macros {
@@ -177,7 +179,9 @@ cfg_if! {
             pub(crate) use expect_wrapper as expect;
         }
     } else {
+        #[allow(unused_imports)]
         pub(crate) use core::{assert, panic, unreachable};
+        #[allow(unused_imports)]
         pub(crate) use macros::{unwrap, expect};
 
         mod macros {
@@ -203,3 +207,9 @@ cfg_if! {
         }
     }
 }
+
+mod private {
+    /// Private sealed trait to seal all GPIO implementations
+    /// which do implement peripheral functionalities.
+    pub trait Sealed {}
+}

src/rcc.rs

@@ -182,7 +182,10 @@ impl APB2 {
     }
 }
 
-const HSI: u32 = 8_000_000; // Hz
+/// Frequency of interal hardware RC oscillator (HSI OSC)
+pub const HSI: Hertz = Hertz(8_000_000);
+/// Frequency of external 32.768 kHz oscillator (LSE OSC)
+pub const LSE: Hertz = Hertz(32_768);
 
 // some microcontrollers do not have USB
 #[cfg(any(feature = "stm32f301", feature = "stm32f318", feature = "stm32f334",))]
@@ -469,7 +472,7 @@ impl CFGR {
         feature = "stm32f398"
     )))]
     fn calc_pll(&self, sysclk: u32) -> (u32, PllConfig) {
-        let pllsrcclk = self.hse.unwrap_or(HSI / 2);
+        let pllsrcclk = self.hse.unwrap_or(HSI.integer() / 2);
         // Get the optimal value for the pll divisor (PLL_DIV) and multiplier (PLL_MUL)
         // Only for HSE PLL_DIV can be changed
         let (pll_mul, pll_div): (u32, Option<u32>) = if self.hse.is_some() {
@@ -545,7 +548,7 @@ impl CFGR {
         feature = "stm32f398",
     ))]
     fn calc_pll(&self, sysclk: u32) -> (u32, PllConfig) {
-        let pllsrcclk = self.hse.unwrap_or(HSI);
+        let pllsrcclk = self.hse.unwrap_or(HSI.integer());
 
         let (pll_mul, pll_div) = {
             // Get the optimal value for the pll divisor (PLL_DIV) and multiplcator (PLL_MUL)
@@ -613,15 +616,17 @@ impl CFGR {
             // Oscillator (max 32 Mhz), without using the PLL.
             (Some(sysclk), Some(hse)) if sysclk == hse => (hse, cfgr::SW_A::HSE, None),
             // No need to use the PLL
-            (Some(sysclk), None) if sysclk == HSI => (HSI, cfgr::SW_A::HSI, None),
+            (Some(sysclk), None) if sysclk == HSI.integer() => {
+                (HSI.integer(), cfgr::SW_A::HSI, None)
+            }
             (Some(sysclk), _) => {
                 let (sysclk, pll_config) = self.calc_pll(sysclk);
                 (sysclk, cfgr::SW_A::PLL, Some(pll_config))
             }
             // Use HSE as system clock
             (None, Some(hse)) => (hse, cfgr::SW_A::HSE, None),
             // Use HSI as system clock
-            (None, None) => (HSI, cfgr::SW_A::HSI, None),
+            (None, None) => (HSI.integer(), cfgr::SW_A::HSI, None),
         }
     }