Should only keep Feb 14th file.

[jpmerten]

Error fixes.

[lukasc-ubc]

This is an experimental feature. The goal is to run a circuit simulation on the design, and return the results for human verification.

✅ Simulation results for EBeam_jpmerten.gds

stdout:

KLayout SiEPIC-Tools version 0.5.29
New version of SiEPIC-Tools is available (0.5.31 vs 0.5.29).
Version check, time: 0.40656089782714844 seconds
SiEPIC-EBeam-PDK Python module: siepic_ebeam_pdk, KLayout technology: EBeam
SiEPIC-EBeam-PDK Python module: pymacros, v0.4.50
Libraries associated with Technology EBeam: ['EBeam', 'EBeam-ANT', 'EBeam-Dream', 'EBeam-SiN', 'EBeam_Beta']
PDK folder: /home/lukasc/.local/lib/python3.10/site-packages/siepic_ebeam_pdk/__init__.py

Found 0 opt-in labels: []
done in 0:00:00.9

📸 Simulation result image(s):

To re-run this simulation, please make a change to the layout file (simply running V verification will change the date stamp in the layout), save it, and upload it to your GitHub fork. This will trigger this simulation to run again.

I hereby grant you permission to use these plots for inclusion in a course report.

• Simulation date: 2026-02-15 11:55:38 PST

[github-actions]

Welcome, new contributor!

Thank you for uploading your design.

If you have not already checked it, please run the SiEPIC Functional Verification in KLayout, using the menu SiEPIC-Verification-Functional Layout Check (V).

We are using GitHub Actions to perform several automated checks. Please ensure that there are no failing checks. Each time you update the files in your fork, this pull request will trigger the automated verification. Check back in a few minutes once they are complete. Click on any failing check indiciated with a red "X" to see the detailed errors.

You may continue making updates to your design, or even contributing additonal designs (using a separate file name), until the tape-out deadline.