·
2 commits
to main
since this release
v1.0-beta.1
redcode
Manuel Sainz de Baranda y Goñi
This tag was signed with the committer’s verified signature.
redcode
Manuel Sainz de Baranda y Goñi
What's Changed
- Removed the interrupt tests (they were included by mistake).
- Fixed the extra clock cycles of
ld ({ix|iy}+d),n. - Fixed the extra clock cycles of
rldandrrd. - Fixed the memory access order in
ex (sp),{hl|ix|iy}. - Fixed the test generator to use the values from the inputs fields.
New Contributors
- @ProdOrDev made their first contribution in #5
- @Frost-Phoenix made their first contribution in #7
Full Changelog: v1.0-beta...v1.0-beta.1
Contributors
Frost-Phoenix and ProdOrDev