Document SpinalHDL facilities used across the org (NaxRiscv, VexiiRiscv, VexRiscv)

source/SpinalHDL/Libraries/bus_slave_factory.rst

@@ -90,4 +90,9 @@ Functionality
      - | Instantiate an internal register which at each cycle do :
        | reg := reg | that
        | Then when a read occur, the register is cleared. This register is readable at ``address`` and placed at ``bitOffset`` in the word
+   * - setOnSet(that,address,bitOffset)
+     - T
+     - | Set bits of ``that`` when the corresponding write bit is ``1``.
+       | Writing a ``1`` to a bit position sets that bit; writing ``0`` has no effect.
+
 

source/SpinalHDL/Libraries/stream.rst

@@ -181,6 +181,15 @@ Functions
        | Modify the payload of the `x` stream, while preserving the `valid` and `ready` signals
      - Stream[T2]
      - 0
+   * - | x.pipelined(pipe: StreamPipe)
+       | x.pipelined(m2s, s2m, halfRate)
+     - | Return a registered version of x cutting combinatorial paths.
+       | ``StreamPipe`` constants: ``NONE`` (no reg), ``M2S`` (cut valid/payload),
+       | ``S2M`` (cut ready), ``FULL`` (cut all), ``HALF`` (cut all, half bandwidth).
+       | Boolean flags: ``m2s`` cuts valid/payload; ``s2m`` cuts ready;
+       | ``halfRate`` cuts all paths at half bandwidth (exclusive with the others).
+     - Stream[T]
+     - varies
 
 
 The following code will create this logic :
@@ -575,6 +584,7 @@ This util take its input stream and routes it to ``outputCount`` stream in a seq
      outputCount = 3
    )
 
+
 StreamTransactionExtender
 ^^^^^^^^^^^^^^^^^^^^^^^^^