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@li041 li041 commented Nov 11, 2025

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Pull Request Overview

This PR fixes a multi-core (SMP) issue on RISC-V by enabling the SUM (Supervisor User Memory) bit during trap initialization, allowing the kernel to access user memory mappings across all CPU cores.

  • Sets the SUM bit in sstatus register during per-CPU trap initialization
  • Ensures consistent kernel-to-user memory access configuration across all cores in SMP systems

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Co-authored-by: Copilot <175728472+Copilot@users.noreply.github.com>
@AsakuraMizu AsakuraMizu merged commit 9b94417 into Starry-OS:main Nov 12, 2025
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2 participants