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calebfletcherdarsor
calebfletcher
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darsor
authored
fix: correct assignment of single bit read-only storage-less fields (#33)
* fix: correct assignment of single bit read-only storage-less fields * add tests for single-bit fields of all types --------- Co-authored-by: Dana Sorensen <dana.r.sorensen@gmail.com>
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-88
lines changed

3 files changed

+156
-88
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‎src/peakrdl_regblock_vhdl/readback/generators.py‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -6,6 +6,7 @@
66
from ..forloop_generator import RDLForLoopGenerator, LoopBody
77

88
from ..utils import do_bitswap, do_slice, get_vhdl_type
9+
from ..vhdl_int import VhdlInt
910

1011
if TYPE_CHECKING:
1112
from ..exporter import RegblockExporter
@@ -155,6 +156,9 @@ def process_reg(self, node: RegNode) -> None:
155156
# the value is in field storage, which may be a std_logic
156157
if field.width == 1:
157158
value = f"to_std_logic_vector({value})"
159+
elif isinstance(value, VhdlInt):
160+
# the value is a constant, ensure it's not reduced to a std_logic
161+
value.allow_std_logic = False
158162

159163
if field.msb < field.lsb:
160164
# Field gets bitswapped since it is in [low:high] orientation

‎tests/test_field_types/regblock.rdl‎

Lines changed: 55 additions & 30 deletions
Original file line numberDiff line numberDiff line change
@@ -2,63 +2,88 @@ addrmap top {
22
default regwidth = 8;
33

44
// All the valid combinations from Table 12
5+
// Test multi-bit and single-bit fields
56
reg {
6-
field {
7-
sw=rw; hw=rw; we; // Storage element
8-
} f[8] = 10;
7+
// Storage element
8+
default sw=rw;
9+
default hw=rw;
10+
default we;
11+
field {} f1[7] = 10;
12+
field {} f2[1] = 0;
913
} r1;
1014

1115
reg {
12-
field {
13-
sw=rw; hw=r; // Storage element
14-
} f[8] = 20;
16+
// Storage element
17+
default sw=rw;
18+
default hw=r;
19+
field {} f1[7] = 20;
20+
field {} f2[1] = 1;
1521
} r2;
1622

1723
reg {
18-
field {
19-
sw=rw; hw=w; wel; // Storage element
20-
} f[8] = 30;
24+
// Storage element
25+
default sw=rw;
26+
default hw=w;
27+
default wel;
28+
field {} f1[7] = 30;
29+
field {} f2[1] = 0;
2130
} r3;
2231

2332
reg {
24-
field {
25-
sw=rw; hw=na; // Storage element
26-
} f[8] = 40;
33+
// Storage element
34+
default sw=rw;
35+
default hw=na;
36+
field {} f1[7] = 40;
37+
field {} f2[1] = 1;
2738
} r4;
2839

2940
reg {
30-
field {
31-
sw=r; hw=rw; we; // Storage element
32-
} f[8] = 50;
41+
// Storage element
42+
default sw=r;
43+
default hw=rw;
44+
default we;
45+
field {} f1[7] = 50;
46+
field {} f2[1] = 0;
3347
} r5;
3448

3549
reg {
36-
field {
37-
sw=r; hw=r; // Wire/Bus - constant value
38-
} f[8] = 60;
50+
// Wire/Bus - constant value
51+
default sw=r;
52+
default hw=r;
53+
field {} f1[7] = 60;
54+
field {} f2[1] = 1;
3955
} r6;
4056

4157
reg {
42-
field {
43-
sw=r; hw=w; // Wire/Bus - hardware assigns value
44-
} f[8];
58+
// Wire/Bus - hardware assigns value
59+
default sw=r;
60+
default hw=w;
61+
field {} f1[7];
62+
field {} f2[1];
4563
} r7;
4664

4765
reg {
48-
field {
49-
sw=r; hw=na; // Wire/Bus - constant value
50-
} f[8] = 80;
66+
// Wire/Bus - constant value
67+
default sw=r;
68+
default hw=na;
69+
field {} f1[7] = 80;
70+
field {} f2[1] = 0;
5171
} r8;
5272

5373
reg {
54-
field {
55-
sw=w; hw=rw; we; // Storage element
56-
} f[8] = 90;
74+
// Storage element
75+
default sw=w;
76+
default hw=rw;
77+
default we;
78+
field {} f1[7] = 90;
79+
field {} f2[1] = 1;
5780
} r9;
5881

5982
reg {
60-
field {
61-
sw=w; hw=r; // Storage element
62-
} f[8] = 100;
83+
// Storage element
84+
default sw=w;
85+
default hw=r;
86+
field {} f1[7] = 100;
87+
field {} f2[1] = 0;
6388
} r10;
6489
};

‎tests/test_field_types/tb_template.sv‎

Lines changed: 97 additions & 58 deletions
Original file line numberDiff line numberDiff line change
@@ -2,130 +2,169 @@
22

33
{% block seq %}
44
{% sv_line_anchor %}
5-
cb.hwif_in.r3.f.wel <= 1;
5+
cb.hwif_in.r3.f1.wel <= 1;
6+
cb.hwif_in.r3.f2.wel <= 1;
67
##1;
78
cb.rst <= '0;
89
##1;
910

1011
// r1 - sw=rw; hw=rw; we; // Storage element
1112
cpuif.assert_read('h0, 10);
12-
assert(cb.hwif_out.r1.f.value == 10);
13-
14-
cpuif.write('h0, 11);
15-
cpuif.assert_read('h0, 11);
16-
assert(cb.hwif_out.r1.f.value == 11);
17-
18-
cb.hwif_in.r1.f.next <= 9;
19-
cpuif.assert_read('h0, 11);
20-
assert(cb.hwif_out.r1.f.value == 11);
21-
cb.hwif_in.r1.f.next <= 12;
22-
cb.hwif_in.r1.f.we <= 1;
13+
assert(cb.hwif_out.r1.f1.value == 10);
14+
assert(cb.hwif_out.r1.f2.value == 0);
15+
16+
cpuif.write('h0, 11 + (1 << 7));
17+
cpuif.assert_read('h0, 11 + (1 << 7));
18+
assert(cb.hwif_out.r1.f1.value == 11);
19+
assert(cb.hwif_out.r1.f2.value == 1);
20+
21+
cb.hwif_in.r1.f1.next <= 9;
22+
cb.hwif_in.r1.f2.next <= 0;
23+
cpuif.assert_read('h0, 11 + (1 << 7));
24+
assert(cb.hwif_out.r1.f1.value == 11);
25+
assert(cb.hwif_out.r1.f2.value == 1);
26+
cb.hwif_in.r1.f1.next <= 12;
27+
cb.hwif_in.r1.f2.next <= 0;
28+
cb.hwif_in.r1.f1.we <= 1;
29+
cb.hwif_in.r1.f2.we <= 1;
2330
@cb;
24-
cb.hwif_in.r1.f.next <= 0;
25-
cb.hwif_in.r1.f.we <= 0;
31+
cb.hwif_in.r1.f1.next <= 0;
32+
cb.hwif_in.r1.f2.next <= 0;
33+
cb.hwif_in.r1.f1.we <= 0;
34+
cb.hwif_in.r1.f2.we <= 0;
2635
cpuif.assert_read('h0, 12);
27-
assert(cb.hwif_out.r1.f.value == 12);
36+
assert(cb.hwif_out.r1.f1.value == 12);
37+
assert(cb.hwif_out.r1.f2.value == 0);
2838

2939

3040
// r2 - sw=rw; hw=r; // Storage element
31-
cpuif.assert_read('h1, 20);
32-
assert(cb.hwif_out.r2.f.value == 20);
41+
cpuif.assert_read('h1, 20 + (1 << 7));
42+
assert(cb.hwif_out.r2.f1.value == 20);
43+
assert(cb.hwif_out.r2.f2.value == 1);
3344

3445
cpuif.write('h1, 21);
3546
cpuif.assert_read('h1, 21);
36-
assert(cb.hwif_out.r2.f.value == 21);
47+
assert(cb.hwif_out.r2.f1.value == 21);
48+
assert(cb.hwif_out.r2.f2.value == 0);
3749

3850

3951
// r3 - sw=rw; hw=w; wel; // Storage element
4052
cpuif.assert_read('h2, 30);
4153

42-
cpuif.write('h2, 31);
43-
cpuif.assert_read('h2, 31);
54+
cpuif.write('h2, 31 + (1 << 7));
55+
cpuif.assert_read('h2, 31 + (1 << 7));
4456

45-
cb.hwif_in.r3.f.next <= 29;
46-
cpuif.assert_read('h2, 31);
47-
cb.hwif_in.r3.f.next <= 32;
48-
cb.hwif_in.r3.f.wel <= 0;
57+
cb.hwif_in.r3.f1.next <= 29;
58+
cb.hwif_in.r3.f2.next <= 0;
59+
cpuif.assert_read('h2, 31 + (1 << 7));
60+
cb.hwif_in.r3.f1.next <= 32;
61+
cb.hwif_in.r3.f2.next <= 0;
62+
cb.hwif_in.r3.f1.wel <= 0;
63+
cb.hwif_in.r3.f2.wel <= 0;
4964
@cb;
50-
cb.hwif_in.r3.f.next <= 0;
51-
cb.hwif_in.r3.f.wel <= 1;
65+
cb.hwif_in.r3.f1.next <= 0;
66+
cb.hwif_in.r3.f2.next <= 0;
67+
cb.hwif_in.r3.f1.wel <= 1;
68+
cb.hwif_in.r3.f2.wel <= 1;
5269
cpuif.assert_read('h2, 32);
5370

5471

5572
// r4 - sw=rw; hw=na; // Storage element
56-
cpuif.assert_read('h3, 40);
73+
cpuif.assert_read('h3, 40 + (1 << 7));
5774
cpuif.write('h3, 41);
5875
cpuif.assert_read('h3, 41);
5976

6077

6178
// r5 - sw=r; hw=rw; we; // Storage element
6279
cpuif.assert_read('h4, 50);
63-
assert(cb.hwif_out.r5.f.value == 50);
80+
assert(cb.hwif_out.r5.f1.value == 50);
6481

65-
cpuif.write('h4, 51);
82+
cpuif.write('h4, 51 + (1 << 7));
6683
cpuif.assert_read('h4, 50);
67-
assert(cb.hwif_out.r5.f.value == 50);
84+
assert(cb.hwif_out.r5.f1.value == 50);
85+
assert(cb.hwif_out.r5.f2.value == 0);
6886

69-
cb.hwif_in.r5.f.next <= 9;
87+
cb.hwif_in.r5.f1.next <= 9;
88+
cb.hwif_in.r5.f2.next <= 1;
7089
cpuif.assert_read('h4, 50);
71-
assert(cb.hwif_out.r5.f.value == 50);
72-
cb.hwif_in.r5.f.next <= 52;
73-
cb.hwif_in.r5.f.we <= 1;
90+
assert(cb.hwif_out.r5.f1.value == 50);
91+
assert(cb.hwif_out.r5.f2.value == 0);
92+
cb.hwif_in.r5.f1.next <= 52;
93+
cb.hwif_in.r5.f2.next <= 1;
94+
cb.hwif_in.r5.f1.we <= 1;
95+
cb.hwif_in.r5.f2.we <= 1;
7496
@cb;
75-
cb.hwif_in.r5.f.next <= 0;
76-
cb.hwif_in.r5.f.we <= 0;
77-
cpuif.assert_read('h4, 52);
78-
assert(cb.hwif_out.r5.f.value == 52);
97+
cb.hwif_in.r5.f1.next <= 0;
98+
cb.hwif_in.r5.f2.next <= 0;
99+
cb.hwif_in.r5.f1.we <= 0;
100+
cb.hwif_in.r5.f2.we <= 0;
101+
cpuif.assert_read('h4, 52 + (1 << 7));
102+
assert(cb.hwif_out.r5.f1.value == 52);
103+
assert(cb.hwif_out.r5.f2.value == 1);
79104

80105

81106
// r6 - sw=r; hw=r; // Wire/Bus - constant value
82-
cpuif.assert_read('h5, 60);
83-
assert(cb.hwif_out.r6.f.value == 60);
107+
cpuif.assert_read('h5, 60 + (1 << 7));
108+
assert(cb.hwif_out.r6.f1.value == 60);
109+
assert(cb.hwif_out.r6.f2.value == 1);
84110
cpuif.write('h5, 61);
85-
cpuif.assert_read('h5, 60);
86-
assert(cb.hwif_out.r6.f.value == 60);
111+
cpuif.assert_read('h5, 60 + (1 << 7));
112+
assert(cb.hwif_out.r6.f1.value == 60);
113+
assert(cb.hwif_out.r6.f2.value == 1);
87114

88115

89116
// r7 - sw=r; hw=w; // Wire/Bus - hardware assigns value
90117
cpuif.assert_read('h6, 0);
91-
cb.hwif_in.r7.f.next <= 70;
92-
cpuif.assert_read('h6, 70);
118+
cb.hwif_in.r7.f1.next <= 70;
119+
cb.hwif_in.r7.f2.next <= 1;
120+
cpuif.assert_read('h6, 70 + (1 << 7));
93121
cpuif.write('h6, 71);
94-
cpuif.assert_read('h6, 70);
122+
cpuif.assert_read('h6, 70 + (1 << 7));
95123

96124

97125
// r8 - sw=r; hw=na; // Wire/Bus - constant value
98126
cpuif.assert_read('h7, 80);
99-
cpuif.write('h7, 81);
127+
cpuif.write('h7, 81 + (1 << 7));
100128
cpuif.assert_read('h7, 80);
101129

102130

103131
// r9 - sw=w; hw=rw; we; // Storage element
104132
cpuif.assert_read('h8, 0);
105-
assert(cb.hwif_out.r9.f.value == 90);
133+
assert(cb.hwif_out.r9.f1.value == 90);
134+
assert(cb.hwif_out.r9.f2.value == 1);
106135

107136
cpuif.write('h8, 91);
108137
cpuif.assert_read('h8, 0);
109-
assert(cb.hwif_out.r9.f.value == 91);
138+
assert(cb.hwif_out.r9.f1.value == 91);
139+
assert(cb.hwif_out.r9.f2.value == 0);
110140

111-
cb.hwif_in.r9.f.next <= 89;
141+
cb.hwif_in.r9.f1.next <= 89;
142+
cb.hwif_in.r9.f2.next <= 1;
112143
cpuif.assert_read('h8, 0);
113-
assert(cb.hwif_out.r9.f.value == 91);
114-
cb.hwif_in.r9.f.next <= 92;
115-
cb.hwif_in.r9.f.we <= 1;
144+
assert(cb.hwif_out.r9.f1.value == 91);
145+
assert(cb.hwif_out.r9.f2.value == 0);
146+
cb.hwif_in.r9.f1.next <= 92;
147+
cb.hwif_in.r9.f2.next <= 1;
148+
cb.hwif_in.r9.f1.we <= 1;
149+
cb.hwif_in.r9.f2.we <= 1;
116150
@cb;
117-
cb.hwif_in.r9.f.next <= 0;
118-
cb.hwif_in.r9.f.we <= 0;
151+
cb.hwif_in.r9.f1.next <= 0;
152+
cb.hwif_in.r9.f2.next <= 0;
153+
cb.hwif_in.r9.f1.we <= 0;
154+
cb.hwif_in.r9.f2.we <= 0;
119155
cpuif.assert_read('h8, 0);
120-
assert(cb.hwif_out.r9.f.value == 92);
156+
assert(cb.hwif_out.r9.f1.value == 92);
157+
assert(cb.hwif_out.r9.f2.value == 1);
121158

122159

123160
// r10 - sw=w; hw=r; // Storage element
124161
cpuif.assert_read('h9, 0);
125-
assert(cb.hwif_out.r10.f.value == 100);
162+
assert(cb.hwif_out.r10.f1.value == 100);
163+
assert(cb.hwif_out.r10.f2.value == 0);
126164

127-
cpuif.write('h9, 101);
165+
cpuif.write('h9, 101 + (1 << 7));
128166
cpuif.assert_read('h9, 0);
129-
assert(cb.hwif_out.r10.f.value == 101);
167+
assert(cb.hwif_out.r10.f1.value == 101);
168+
assert(cb.hwif_out.r10.f2.value == 1);
130169

131170
{% endblock %}

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