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Add force-empty hwif_in/hwif_out generation options build #67: Pull request #39 opened by Topi-ab
Action required Topi-ab:feature/force-empty-hwif-ports
Topi-ab:feature/force-empty-hwif-ports
Action required
v1.2.0.0 build #64: Release v1.2.0.0+vhdl published by darsor
2m 52s
2m 52s
fix read-buffered signed/fixedpoint fields build #63: Commit 44cda50 pushed by darsor
1m 28s main
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1m 28s
fix read/write buffering in arrays of regfiles (#31) build #62: Commit 9e067e0 pushed by darsor
1m 21s main
main
1m 21s
fix: correct assignment of single bit read-only storage-less fields (… build #61: Commit 23a2ce3 pushed by darsor
1m 20s main
main
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fix: correct assignment of single bit read-only storage-less fields build #60: Pull request #33 synchronize by darsor
1m 23s calebfletcher:fix-ro-singlebit-storageless
calebfletcher:fix-ro-singlebit-storageless
1m 23s
include hdl-src files in python wheel (#30) build #59: Commit adcd3dd pushed by darsor
1m 20s main
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1m 20s
command line flag to copy reg_utils.vhd (#30) build #58: Commit f987793 pushed by darsor
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58s
fix external block address width bug (#29) build #57: Commit 783eade pushed by darsor
1m 20s main
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1m 20s
clarified upstream bugfix handling in issue template build #56: Commit 592f779 pushed by darsor
1m 22s main
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1m 22s
fix jinja syntax error build #55: Commit 7482bc4 pushed by darsor
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1m 26s
fix python versions <3.9 build #54: Commit 9d74db5 pushed by darsor
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Merge upstream/v1.2.0 into VHDL port build #53: Commit b54a576 pushed by darsor
1m 7s main
main
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fix: correct assignment of single bit read-only storage-less fields build #52: Pull request #33 opened by calebfletcher
1m 25s calebfletcher:fix-ro-singlebit-storageless
calebfletcher:fix-ro-singlebit-storageless
1m 25s
Single-bit std_logic to a slice (ghdl) (#28) build #51: Commit 0743208 pushed by darsor
1m 25s main
main
1m 25s
Single-bit std_logic to a slice (ghdl) build #50: Pull request #28 synchronize by davekeeshan
1m 38s daxzio:single2slice
daxzio:single2slice
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Switch to LGPLv3 license (#24) build #49: Commit 91895d5 pushed by darsor
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main
1m 17s
Single-bit std_logic to a slice (ghdl) build #48: Pull request #28 opened by davekeeshan
1m 27s daxzio:single2slice
daxzio:single2slice
1m 27s
Skip read/write buffering for external components build #47: Pull request #26 opened by davekeeshan
1m 19s daxzio:skiprwexternal
daxzio:skiprwexternal
1m 19s
Switch to LGPLv3 license build #46: Pull request #24 opened by amykyta3
1m 21s dev/LGPLv3
dev/LGPLv3
1m 21s
Switch to LGPLv3 license build #45: Commit fded497 pushed by amykyta3
1m 25s dev/LGPLv3
dev/LGPLv3
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v1.1.1.0 build #44: Release v1.1.1.0+vhdl published by darsor
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2m 13s
Merge upstream/v1.1.1 into VHDL port build #43: Commit 2238b14 pushed by darsor
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1m 27s
v1.1.0.0 build #42: Release v1.1.0.0+vhdl published by darsor
2m 13s
2m 13s
Merge upstream/v1.1.0 into VHDL port build #41: Commit 68d199f pushed by darsor
1m 34s main
main
1m 34s