Skip read/write buffering for external components

[davekeeshan]

Description of change

Fixes #25. Read/write-buffering logic is no longer emitted for external components.

Checklist

• I have reviewed this project's contribution guidelines
• This change has been tested and does not break any of the existing unit tests. (if unable to run the tests, let us know)
• If this change adds new features, I have added new unit tests that cover them.

[darsor]

Thanks for the PR! It looks like this addresses two separate issues: #26 and an unreported bug regarding external blocks with address widths of 1 (or 0?).

• Skip read/write buffering for external components #26 will get fixed with the latest merge from the upstream systemverilog repository
• Please open a new issue describing the address width bug. I think the best way to handle this would be to ensure the address is always a std_logic_vector, but it looks like that would require some more refactoring. I can look into it if you like. New tests should be added to avoid regressions.

[davekeeshan]

I have opened a new issue #29 to capture the address width issue, if you have an upstream merge that will fix the read/write issue for external components close this PR

[darsor]

#25 was resolved from an upstream merge.