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fix jinja syntax error
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tests/lib/vhdl_adapter/test_adapter_tmpl.sv

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Original file line numberDiff line numberDiff line change
@@ -31,7 +31,7 @@ module regblock_adapter_sv
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regblock_adapter_vhdl
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{%- if sv_cpuif.parameters %} #(
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{%- for param in sv_cpuif.parameters %}
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{%- set param_name = param[len("parameter"):].split("=")[0].strip() %}
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{%- set param_name = param[("parameter" | length):].split("=")[0].strip() %}
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.{{param_name}}({{param_name}}){% if not loop.last %},{% endif %}
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{%- endfor %}
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)

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