fix read-buffered signed/fixedpoint fields

darsor · darsor · commit 44cda5074e84 · 2025-12-28T16:38:23.000Z
diff --git a/src/peakrdl_regblock_vhdl/field_logic/hw_write.py b/src/peakrdl_regblock_vhdl/field_logic/hw_write.py
@@ -1,6 +1,7 @@
 from typing import TYPE_CHECKING, List
 
 from .bases import NextStateConditional, NextStateUnconditional
+from ..utils import get_vhdl_type
 
 if TYPE_CHECKING:
     from systemrdl.node import FieldNode
@@ -23,7 +24,12 @@ def is_match(self, field: 'FieldNode') -> bool:
     def get_assignments(self, field: 'FieldNode') -> List[str]:
         hwmask = field.get_property('hwmask')
         hwenable = field.get_property('hwenable')
-        I = str(self.exp.hwif.get_input_identifier(field))
+        I = self.exp.hwif.get_input_identifier(field)
+        vhdl_type = get_vhdl_type(field)
+        if field.width == 1 and vhdl_type != "std_logic":
+            I = f"to_std_logic({I})"
+        if field.width > 1 and vhdl_type != "std_logic_vector":
+            I = f"to_std_logic_vector({I})"
         R = self.exp.field_logic.get_storage_identifier(field)
         if hwmask is not None:
             M = self.exp.dereferencer.get_value(hwmask)
@@ -32,7 +38,7 @@ def get_assignments(self, field: 'FieldNode') -> List[str]:
             E = self.exp.dereferencer.get_value(hwenable)
             next_val = f"({I} and {E}) or ({R} and not {E})"
         else:
-            next_val = I
+            next_val = str(I)
 
         return [
             f"next_c := {next_val};",
@@ -44,7 +50,12 @@ class _QualifiedWrite(NextStateConditional):
     def get_assignments(self, field: 'FieldNode') -> List[str]:
         hwmask = field.get_property('hwmask')
         hwenable = field.get_property('hwenable')
-        I = str(self.exp.hwif.get_input_identifier(field))
+        I = self.exp.hwif.get_input_identifier(field)
+        vhdl_type = get_vhdl_type(field)
+        if field.width == 1 and vhdl_type != "std_logic":
+            I = f"to_std_logic({I})"
+        if field.width > 1 and vhdl_type != "std_logic_vector":
+            I = f"to_std_logic_vector({I})"
         R = self.exp.field_logic.get_storage_identifier(field)
         if hwmask is not None:
             M = self.exp.dereferencer.get_value(hwmask)
@@ -53,7 +64,7 @@ def get_assignments(self, field: 'FieldNode') -> List[str]:
             E = self.exp.dereferencer.get_value(hwenable)
             next_val = f"({I} and {E}) or ({R} and not {E})"
         else:
-            next_val = I
+            next_val = str(I)
 
         return [
             f"next_c := {next_val};",
diff --git a/src/peakrdl_regblock_vhdl/read_buffering/implementation_generator.py b/src/peakrdl_regblock_vhdl/read_buffering/implementation_generator.py
@@ -4,6 +4,8 @@
 from systemrdl.node import RegNode
 
 from ..forloop_generator import RDLForLoopGenerator
+from ..utils import do_bitswap, get_vhdl_type
+from ..vhdl_int import VhdlInt
 
 if TYPE_CHECKING:
     from . import ReadBuffering
@@ -42,13 +44,23 @@ def get_assignments(self, node: RegNode) -> str:
                 s.append(f"{data}({field.low-1} downto {bidx}) <= (others => '0');")
 
             value = self.exp.dereferencer.get_value(field)
+            if self.exp.hwif.has_value_input(field) and not field.implements_storage:
+                # the value is a hwif input, which may not be a std_logic_vector, convert it
+                if get_vhdl_type(field) != "std_logic_vector":
+                    value = f"to_std_logic_vector({value})"
+            elif field.implements_storage:
+                # the value is in field storage, which may be a std_logic
+                if field.width == 1:
+                    value = f"to_std_logic_vector({value})"
+            elif isinstance(value, VhdlInt):
+                # the value is a constant, ensure it's not reduced to a std_logic
+                value.allow_std_logic = False
+
             if field.msb < field.lsb:
                 # Field gets bitswapped since it is in [low:high] orientation
-                value = f"bitswap({value})"
-            if field.high == field.low:
-                s.append(f"{data}({field.high}) <= {value};")
-            else:
-                s.append(f"{data}({field.high} downto {field.low}) <= {value};")
+                value = do_bitswap(value)
+
+            s.append(f"{data}({field.high} downto {field.low}) <= {value};")
 
             bidx = field.high + 1
 
diff --git a/src/peakrdl_regblock_vhdl/readback/generators.py b/src/peakrdl_regblock_vhdl/readback/generators.py
@@ -224,6 +224,19 @@ def process_buffered_reg_with_bypass(self, node: RegNode, regwidth: int, accessw
                 # insert padding before
                 self.add_content(f"readback_array({self.current_offset_str})({field.low - 1} downto {bidx}) <= (others => '0');")
 
+            value = self.exp.dereferencer.get_value(field)
+            if self.exp.hwif.has_value_input(field) and not field.implements_storage:
+                # the value is a hwif input, which may not be a std_logic_vector, convert it
+                if get_vhdl_type(field) != "std_logic_vector":
+                    value = f"to_std_logic_vector({value})"
+            elif field.implements_storage:
+                # the value is in field storage, which may be a std_logic
+                if field.width == 1:
+                    value = f"to_std_logic_vector({value})"
+            elif isinstance(value, VhdlInt):
+                # the value is a constant, ensure it's not reduced to a std_logic
+                value.allow_std_logic = False
+
             if field.high >= accesswidth:
                 # field gets truncated
                 r_low = field.low
@@ -237,22 +250,19 @@ def process_buffered_reg_with_bypass(self, node: RegNode, regwidth: int, accessw
                     f_low = field.width - 1 - f_low
                     f_high = field.width - 1 - f_high
                     f_low, f_high = f_high, f_low
-                    value = do_bitswap(do_slice(self.exp.dereferencer.get_value(field), f_high, f_low, reduce=False))
+                    value = do_slice(value, f_high, f_low, reduce=False)
+                    value = do_bitswap(value)
                 else:
-                    value = do_slice(self.exp.dereferencer.get_value(field), f_high, f_low, reduce=False)
+                    value = do_slice(value, f_high, f_low, reduce=False)
 
                 self.add_content(f"readback_array({self.current_offset_str})({r_high} downto {r_low}) <= {value} when {rd_strb} else (others => '0');")
                 bidx = accesswidth
             else:
                 # field fits in subword
-                value = self.exp.dereferencer.get_value(field)
                 if field.msb < field.lsb:
                     # Field gets bitswapped since it is in [low:high] orientation
                     value = do_bitswap(value)
 
-                if field.width == 1:
-                    # convert from std_logic to std_logic_vector
-                    value = f"to_std_logic_vector({value})"
                 self.add_content(f"readback_array({self.current_offset_str})({field.high} downto {field.low}) <= {value} when {rd_strb} else (others => '0');")
                 bidx = field.high + 1
 
diff --git a/tests/test_read_buffer/regblock.rdl b/tests/test_read_buffer/regblock.rdl
@@ -129,10 +129,6 @@ addrmap top {
     //--------------------------------------------------------------------------
 
     regfile {
-      reg {
-        field {} rst = 0;
-      } reset;
-
       reg {
         regwidth = 128;
         buffer_reads;
@@ -144,4 +140,29 @@ addrmap top {
         field {} f4[1];
       } fields;
     } regfile_array[2];
+
+    //--------------------------------------------------------------------------
+    // signed/fixed-point
+    //--------------------------------------------------------------------------
+
+    reg {
+        regwidth = 32;
+        buffer_reads;
+        default sw = r;
+        default hw = w;
+
+        // ensure the various VHDL types (signed, ufixed, etc.) work with
+        // multi- and single-bit fields, as well as different field access types
+
+        // first word is treated separately to implement a read pass-through
+        field {is_signed; sw=rw; }        f1[1];
+        field {is_signed; }               f2[1];
+        field {is_signed; }               f3[6];
+
+        field {fracwidth=1; sw=rw; we; }  f4[8] = 111;
+        field {fracwidth=1; hw=r; }       f5[8] = 222;
+        field {is_signed; }               f6[1];
+        field {fracwidth=1; sw=rw; wel; } f7[1] = 0;
+        field {fracwidth=1; hw=r; }       f8[1] = 1;
+    } reg_fp;
 };
diff --git a/tests/test_write_buffer/regblock.rdl b/tests/test_write_buffer/regblock.rdl
@@ -117,19 +117,30 @@ addrmap top {
     //--------------------------------------------------------------------------
 
     regfile {
-      reg {
-        field {} rst = 0;
-      } reset;
-
       reg {
         regwidth = 128;
         buffer_writes;
-        default sw = w;
+        default sw = rw;
         default hw = r;
         field {} f1[16] = 0;
         field {} f2[32] = 0;
         field {} f3[64] = 0;
         field {} f4[1] = 0;
       } fields;
     } regfile_array[2];
+
+    //--------------------------------------------------------------------------
+    // signed/fixed-point
+    //--------------------------------------------------------------------------
+
+    reg {
+        regwidth = 32;
+        buffer_writes;
+        default sw = rw;
+        default hw = r;
+        field {is_signed; } f1[8] = 111;
+        field {fracwidth=1; } f2[8] = 222;
+        field {is_signed; } f3[1] = 0;
+        field {fracwidth=1; } f4[1] = 1;
+    } reg_fp;
 };
