command line flag to copy reg_utils.vhd (#30)

Author: darsor

MANIFEST.in

@@ -1,2 +1,3 @@
 recursive-include src/peakrdl_regblock_vhdl *.vhd
+recursive-include hdl-src *.vhd
 prune tests

src/peakrdl_regblock_vhdl/__peakrdl__.py

@@ -24,6 +24,7 @@ class Exporter(ExporterSubcommandPlugin):
         "default_reset": schema.Choice(["rst", "rst_n", "arst", "arst_n"]),
         "err_if_bad_addr": schema.Boolean(),
         "err_if_bad_rw": schema.Boolean(),
+        "copy_utils_pkg": schema.Boolean(),
     }
 
     @functools.lru_cache()
@@ -161,6 +162,13 @@ def add_exporter_arguments(self, arg_group: 'argparse._ActionsContainer') -> Non
             performed to a read-only or write-only register."""
         )
 
+        arg_group.add_argument(
+            "--copy-utils-pkg",
+            action="store_true",
+            default=False,
+            help="Copy the reg_utils.vhd package into the output directory."
+        )
+
     def do_export(self, top_node: 'AddrmapNode', options: 'argparse.Namespace') -> None:
         cpuifs = self.get_cpuifs()
 
@@ -224,5 +232,6 @@ def do_export(self, top_node: 'AddrmapNode', options: 'argparse.Namespace') -> N
             default_reset_activelow=default_reset_activelow,
             err_if_bad_addr=options.err_if_bad_addr or self.cfg['err_if_bad_addr'],
             err_if_bad_rw=options.err_if_bad_rw or self.cfg['err_if_bad_rw'],
+            copy_utils_pkg=options.copy_utils_pkg,
             default_reset_async=default_reset_async,
         )

src/peakrdl_regblock_vhdl/exporter.py

@@ -1,4 +1,5 @@
 import os
+import shutil
 from typing import TYPE_CHECKING, Union, Any, Type, Optional, Set, List
 from collections import OrderedDict
 
@@ -126,6 +127,8 @@ def export(self, node: Union[RootNode, AddrmapNode], output_dir:str, **kwargs: A
             If overriden to True: If an illegal access is performed to a read-only or write-only
             register, the CPUIF response signal shows an error. For example: APB.PSLVERR = 1'b1,
             AXI4LITE.*RESP = 2'b10.
+        copy_utils_pkg: bool
+            If overridden to True, copy the reg_utils.vhd package into the output directory.
         """
         # If it is the root node, skip to top addrmap
         if isinstance(node, RootNode):
@@ -201,6 +204,12 @@ def export(self, node: Union[RootNode, AddrmapNode], output_dir:str, **kwargs: A
         stream = template.stream(context)
         stream.dump(module_file_path)
 
+        if self.ds.copy_utils_pkg:
+            shutil.copyfile(
+                os.path.join(os.path.dirname(__file__), "..", "..", "hdl-src", "reg_utils.vhd"),
+                os.path.join(output_dir, "reg_utils.vhd")
+            )
+
         if hwif_report_file:
             hwif_report_file.close()
 
@@ -280,6 +289,9 @@ def __init__(self, top_node: AddrmapNode, kwargs: Any) -> None:
         self.err_if_bad_addr = kwargs.pop("err_if_bad_addr", False) # type: bool
         self.err_if_bad_rw = kwargs.pop("err_if_bad_rw", False) # type: bool
 
+        # General exporter options
+        self.copy_utils_pkg = kwargs.pop("copy_utils_pkg", False) # type: bool
+
         #------------------------
         # Info about the design
         #------------------------

tests/lib/base_testcase.py

@@ -108,9 +108,9 @@ def export_regblock(self):
         rdlc.compile_file(rdl_file)
         root = rdlc.elaborate(self.rdl_elab_target, "regblock", self.rdl_elab_params)
 
-        for lang, exporter, cpuif_cls in (
-            ("", self.sv_exporter, self.cpuif.sv_cpuif_cls),
-            ("vhdl_", self.vhdl_exporter, self.cpuif.vhdl_cpuif_cls),
+        for lang, exporter, cpuif_cls, kwargs in (
+            ("", self.sv_exporter, self.cpuif.sv_cpuif_cls, {}),
+            ("vhdl_", self.vhdl_exporter, self.cpuif.vhdl_cpuif_cls, {"copy_utils_pkg": True}),
         ):
             exporter.export(
                 root,
@@ -129,6 +129,7 @@ def export_regblock(self):
                 default_reset_async=self.default_reset_async,
                 err_if_bad_addr=self.err_if_bad_addr,
                 err_if_bad_rw=self.err_if_bad_rw,
+                **kwargs,
         )
         vhdl_adapter = VhdlAdapter(self.sv_exporter, self.vhdl_exporter, self.cpuif)
         vhdl_adapter.export(self.get_run_dir())

tests/lib/simulators/base.py

@@ -33,7 +33,7 @@ def vhdl_tb_files(self) -> List[str]:
         files = []
         files.extend(file for file in self.testcase.cpuif.get_sim_files() if file.endswith(".vhd"))
         files.extend(file for file in self.testcase.get_extra_tb_files() if file.endswith(".vhd"))
-        files.append("../../../../hdl-src/reg_utils.vhd")
+        files.append("reg_utils.vhd")
         files.append("vhdl_regblock_pkg.vhd")
         files.append("vhdl_regblock.vhd")
         files.append("regblock_adapter.vhd")