Create testbench.sv

Author: Tan12d

LAB VII: CONSTRUCT, TEST AND INVESTIGATE THE OPERATION OF VARIOUS FLIP-FLOP CIRCUITS USING HDL/Q3/testbench.sv

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+module testbench_JKFF;
+  reg   t_s, t_r, t_q;
+  wire  t_t;
+  circuit3 dut(t_s, t_r, t_q, t_t);
+
+  initial
+    begin
+      $dumpfile("dump.vcd");
+      $dumpvars(0, dut);
+
+      #1
+      t_s <= 0;
+      t_r <= 0;
+      t_q <= 0;
+
+      #1
+      t_s <= 0;
+      t_r <= 0;
+      t_q <= 1;
+
+      #1
+      t_s <= 0;
+      t_r <= 1;
+      t_q <= 0;
+
+      #1
+      t_s <= 0;
+      t_r <= 1;
+      t_q <= 1;
+
+      #1
+      t_s <= 1;
+      t_r <= 0;
+      t_q <= 0;
+
+      #1
+      t_s <= 1;
+      t_r <= 0;
+      t_q <= 1;
+
+      #1
+      t_s <= 1;
+      t_r <= 1;
+      t_q <= 0;
+
+      #1
+      t_s <= 1;
+      t_r <= 1;
+      t_q <= 1;
+
+      #1
+      
+      $finish();
+    end
+endmodule