feat: add RISC-V 64-bit (riscv64) architecture support#223
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carlosqwqqwq wants to merge 1 commit intoTencent:masterfrom
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feat: add RISC-V 64-bit (riscv64) architecture support#223carlosqwqqwq wants to merge 1 commit intoTencent:masterfrom
carlosqwqqwq wants to merge 1 commit intoTencent:masterfrom
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Implement native context switching for RISC-V 64-bit (riscv64) following the LP64D calling convention. Changes: - coctx.h: add regs[16] for riscv64 (14 callee-saved regs + a0/a1 for argument passing) - coctx.cpp: add coctx_make() and coctx_init() for riscv64, initializing ra (entry point), sp (stack pointer), s0 (frame pointer), and a0/a1 (function arguments) - coctx_swap.S: add riscv64 assembly for coctx_swap(), saving/restoring ra, sp, s0-s11, a0, a1 per the RISC-V LP64D ABI This enables libco to compile and run on riscv64 platforms. Verified on OBS (openSUSE Tumbleweed) for both x86_64 and riscv64.
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Implement native context switching for RISC-V 64-bit (riscv64) following the LP64D calling convention.
Changes:
This enables libco to compile and run on riscv64 platforms. Verified on OBS (openSUSE Tumbleweed) for both x86_64 and riscv64.