Skip to content

Conversation

@Siddharth-Vadapalli-at-TI
Copy link
Collaborator

The Cadence PCIe Controller supports 64-Bit Address Space on the following K3 SoCs:
AM64, AM68, AM69, J7200, J721E, J721S2, J722S, J742S2 and J784S4.

The 64-Bit Address Space provides a larger 4 GB region compared to the 128 MB region in the 32-Bit Address Space. Since the Linux device-tree for the aforementioned SoCs has been updated to switch to the 64-Bit Address Space, document it.

…pace

The Cadence PCIe Controller supports 64-Bit Address Space on the following
K3 SoCs:
    AM64, AM68, AM69, J7200, J721E, J721S2, J722S, J742S2 and J784S4.

The 64-Bit Address Space provides a larger 4 GB region compared to the
128 MB region in the 32-Bit Address Space. Since the Linux device-tree for
the aforementioned SoCs has been updated to switch to the 64-Bit Address
Space, document it.

Signed-off-by: Siddharth Vadapalli <[email protected]>
@praneethbajjuri praneethbajjuri merged commit 63143fa into TexasInstruments:master Jun 4, 2025
4 checks passed
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment

Labels

None yet

Projects

None yet

Development

Successfully merging this pull request may close these issues.

6 participants