Bugfix/nbs

source/buildroot/Overview.rst

@@ -51,14 +51,14 @@ Repository structure
     ├── external.mk
     ├── Config.in 
     ├── board
-    │   ├── ti
-    │   │   ├── am62x-sk
-    │   │   ├── common
+    │   ├── ti
+    │   │   ├── am62x-sk
+    │   │   ├── common
     ├── COPYING
     ├── README.md
     ├── configs
-    │   ├── ti_release_am62x_sk_defconfig
-    │   └── ti_release_am62x_sk_rt_defconfig
+    │   ├── ti_release_am62x_sk_defconfig
+    │   └── ti_release_am62x_sk_rt_defconfig
 
 :file:`external.desc`: contains name and description of br2-external tree.
 

source/common/EVM_Hardware_Setup/_66AK2G02_GP_EVM_Hardware_Setup.rst

@@ -220,7 +220,7 @@ power supply connected to the DC power jack (J3). Internally, +12V input
 is converted into required voltage levels using local DC-DC converters
 
 Please note that a power supply is included with the 66AK2GX Evaluation
-Module. The power supply has the following specs :
+Module. The power supply has the following specs :
 
 -  12V DC output
 -  5A output
@@ -234,7 +234,7 @@ Module. The power supply has the following specs :
 This section describes the setup to connect to 66AK2GX GP EVM using
 Code composer Studio environment and an emulator.
 
-There are two scenarios while connecting to the EVM :
+There are two scenarios while connecting to the EVM :
 
 -  **Connect to EVM without a SD card boot image to boot the EVM**
 -  **Connect to EVM after booting an image from the SD card**.
@@ -330,7 +330,7 @@ provided below:
 .. rubric:: Connecting to target
    :name: connecting-to-target
 
-**Step1 :** Download Code composer Studio v6.1.3 or for CCSv6.1.2 and
+**Step1 :** Download Code composer Studio v6.1.3 or for CCSv6.1.2 and
 earlier, ensure it contains Keystone device support package version
 1.1.5 as described in the how to guide
 

source/common/EVM_Hardware_Setup/_66AK2G02_ICE_EVM_Hardware_setup.rst

@@ -136,7 +136,7 @@ CCS Setup
 This section describes the setup to connect to 66AK2G02 ICE EVM using
 Code composer Studio environment and an emulator.
 
-There are two scenarios while connecting to the EVM :
+There are two scenarios while connecting to the EVM :
 
 -  **Connect to EVM without a SD card boot image to boot the EVM**
 -  **Connect to EVM after booting an image from the SD card**.

source/common/EVM_Hardware_Setup/_AM572x_GP_EVM_Hardware_Setup.rst

@@ -160,7 +160,7 @@ scenario, the SBL component provides the same functionality
 .. rubric:: CCS Setup
    :name: ccs-setup
 
-There are two scenarios while connecting to the EVM :
+There are two scenarios while connecting to the EVM :
 
 -  **Connect to EVM without a SD card boot image to boot the EVM**
 -  **Connect to EVM after booting an image from the SD card**.
@@ -207,7 +207,7 @@ provided below:
 .. rubric:: Connecting to target
    :name: connecting-to-target
 
-**Step1 :** Download Code composer Studio and AM572x Sitara CSP package
+**Step1 :** Download Code composer Studio and AM572x Sitara CSP package
 as described in the wiki article mentioned below:
 
 `Install Code composer Studio v6 for
@@ -301,7 +301,7 @@ in the previous section.
     CortexA15_0: GEL Output:        PHY_STATUSx registers
     CortexA15_0: GEL Output:        Two EMIFs in interleaved mode - (2GB total)
     CortexA15_0: GEL Output: --->>> DDR3 Initialization is DONE! <<<---
-    CortexA15_0: GEL Output: --->>> AM572x Target Connect Sequence DONE !!!!!  <<<---
+    CortexA15_0: GEL Output: --->>> AM572x Target Connect Sequence DONE !!!!!  <<<---
     CortexA15_0: GEL Output: --->>> IPU1SS Initialization is in progress ... <<<---
     CortexA15_0: GEL Output: --->>> IPU1SS Initialization is DONE! <<<---
     CortexA15_0: GEL Output: --->>> IPU2SS Initialization is in progress ... <<<---

source/common/EVM_Hardware_Setup/_AM62Px_EVM_Hardware_Setup.rst

@@ -4,7 +4,7 @@ AM62Px SK EVM Hardware Setup
 .. rubric:: Description
 
 The AM62Px starter kit (SK) evaluation module (EVM) is a stand-alone test and development platform
-built around the AM62Px system-on-a-chip (SoC). AM62Px processors are comprised of a quad-core 64-bit
+built around the AM62Px system-on-a-chip (SoC). AM62Px processors are comprised of a quad-core 64-bit
 Arm®-Cortex®-A53 microprocessor, dual-core Arm Cortex-R5F microcontroller (MCU).
 
 To know more on how to quickly start Linux on the AM62Px Starter Kit EVM (SK EVM) and run out-of-box demos, you can refer `AM62Px Starter Kit EVM Quick Start Guide. <https://tgrex19.toro.design.ti.com/tirex/explore/node?node=A__AaM8dWF78x986JGiasfPsA__am62px-devtools__FUz-xrs__LATEST>`__

source/common/EVM_Hardware_Setup/_AM62x_EVM_Hardware_Setup.rst

@@ -4,7 +4,7 @@ AM62x SK EVM Hardware Setup
 .. rubric:: Description
 
 The AM62x starter kit (SK) evaluation module (EVM) is a stand-alone test and development platform
-built around the AM62x system-on-a-chip (SoC). AM62x processors are comprised of a quad-core 64-bit
+built around the AM62x system-on-a-chip (SoC). AM62x processors are comprised of a quad-core 64-bit
 Arm®-Cortex®-A53 microprocessor, single-core Arm Cortex-R5F microcontroller (MCU) and an Arm
 Cortex-M4F MCU.
 

source/common/EVM_Hardware_Setup/_AM64x_EVM_Hardware_Setup.rst

@@ -24,7 +24,7 @@ headers, multiple boot options and flexible debug capabilities.The starter kit
 is equipped with AM64x processor and an optimized feature-set to allow the user
 to create commercial and industrial solutions using Ethernet-based, USB, and
 serial wired interfaces, two Ethernet Ports for wired connectivity. Using standard
-serial protocols such as UART, I²C, and SPI, the starter kit can interface with
+serial protocols such as UART, I2C, and SPI, the starter kit can interface with
 a multitude of other devices, acting as a communications gateway.
 
 For Quick Start Quide `click here. <https://dev.ti.com/tirex/content/tirex-product-tree/am64x-devtools/docs/am64x_skevm_quick_start_guide.html>`__

source/common/EVM_Hardware_Setup/_EVMK2H_Hardware_Setup.rst

@@ -18,7 +18,7 @@ of the emulator daughter card. The driver can be downloaded from here
 
 .. note:: Before testing the usb connection, make sure that the mini-usb cable is plugged into the port on the base board. (and not connected to the daughter card).
 
-After installing the driver and connecting the USB cable, two COM ports
+After installing the driver and connecting the USB cable, two COM ports
 should be visible in the list of COM ports available to connect to in
 the PC Host terminal console. The lower COM port corresponds to the SoC
 UART and the higher one corresponds to the MCU UART.
@@ -237,7 +237,7 @@ with the following steps.
 #. Select the BMC COM Port (the same COM port used to issue the ver
    command earlier), and set the ‘Baud Rate’ to 115200.
 #. Set ‘Transfer Size’ to 60, and make sure ‘Disable Auto Baud Support’
-   is unchecked. 
+   is unchecked.
 
    .. image::  /images/LMflashProg_Config.png
 
@@ -652,5 +652,5 @@ Connecting Target...
     arm_A15_0: GEL Output: A15 non secure mode entered
 
 Users can now load and run code on the cores by using Run -> Load
-Program. Happy Debugging !!
+Program. Happy Debugging !!
 

source/common/EVM_Hardware_Setup/_J722S_EVM_Hardware_Setup.rst

@@ -4,7 +4,7 @@ J722S EVM Hardware Setup
 .. rubric:: Description
 
 The J722S evaluation module (or TDA4VEN and AM67 EVM) is a stand-alone test and development platform
-built around the J722S system-on-a-chip (SoC). J722S processors are comprised of a quad-core 64-bit
+built around the J722S system-on-a-chip (SoC). J722S processors are comprised of a quad-core 64-bit
 Arm®-Cortex®-A53 microprocessor, dual-core Arm Cortex-R5F microcontroller (MCU).
 The EVM gives developers the basic resources needed for most general‐purpose type projects.
 

source/common/EVM_Hardware_Setup/_OMAPL137_EVM_Hardware_Setup.rst

@@ -77,7 +77,7 @@ Target Configuration
 .. Image:: /images/OMAPL137_targetConfig.png
 
 
--  Check "OMAPL137" or "C6747" as Device and save. 
+-  Check "OMAPL137" or "C6747" as Device and save.
 
 .. Tip:: If you don't see "OMAPL137", ensure that you have installed CCS and selected Single Core DSP devices in the installation.
 

source/common/EVM_Hardware_Setup/_TMDSEVM6657L_EVM_Hardware_Setup.rst

@@ -57,7 +57,7 @@ The application needs an IP address. It can use either a static IP
 address (pre-configured) or it can request one using DHCP. This is
 controlled by setting dip switch 2 of SW9.
 
-| User Switch 2 ON : DHCP
+| User Switch 2 ON : DHCP
 |  User Switch 2 OFF: Static IP
 
 .. image:: /images/TMD6678LSW9.png
@@ -95,7 +95,7 @@ Boot Mode Dip Switch Settings
 
 The EVM supports booting image from various devices (EEPROM, NAND or
 NOR) via IBL (at I2C address 0x51), I2C EEPROM (at I2C address 0x50),
-and ROM Boot modes (such as Ethernet, SRIO, PCIe, SPI etc.) which
+and ROM Boot modes (such as Ethernet, SRIO, PCIe, SPI etc.) which
 address the boot source directly from the ROM code. Below is the table
 showing the boot mode dip switch settings for different boot mode that
 the EVM supports:
@@ -106,7 +106,7 @@ the EVM supports:
 |                          | (Pin1, 2, 3, 4, 5, 6, 7, | (Pin1, 2, 3, 4, 5, 6, 7, |
 |                          | 8)                       | 8)                       |
 +==========================+==========================+==========================+
-| IBL NOR boot on image 0  | (off, off, on, off, on,  | (on, on, on, off, on,    |
+| IBL NOR boot on image 0  | (off, off, on, off, on,  | (on, on, on, off, on,    |
 | (default)                | on, on,                  | on, on, on)\ :sup:`4`    |
 |                          | on)\ :sup:`1,2,3`        |                          |
 +--------------------------+--------------------------+--------------------------+
@@ -145,22 +145,22 @@ the EVM supports:
 
 **Footnotes:**
 
-|  1. Pin 1 of SW3 is the endian pin, by default, it is set to off (Little Endian) 
+|  1. Pin 1 of SW3 is the endian pin, by default, it is set to off (Little Endian)
 |
 
-|  2. Pin 2-4 of SW3 are the boot mode pins, by default it is set to I2C boot mode (off, on, off)
+|  2. Pin 2-4 of SW3 are the boot mode pins, by default it is set to I2C boot mode (off, on, off)
 |
 
 |  3. Pin 5-8 of SW3 and pin 1-2 of SW5 are the boot parameter index pins for I2C boot (paramter index 0/1 for NOR boot image 0/1, parameter index 2/3 for NAND boot image 0/1, parameter index 4 for TFTP boot). By default, image 0 is programmed to offset byte address 0x0 on NOR, and 0x20000 (block 1 start address) on NAND, image 1 is programmed to offset byte address 0x4000000 on NAND.
 |
 
-|  4. Pin 4 of SW5 is the I2C address pin (off: 0x51, on: 0x50)  for I2C boot mode
+|  4. Pin 4 of SW5 is the I2C address pin (off: 0x51, on: 0x50)  for I2C boot mode
 |
 
 |  5. This will set the board to boot from SRIO boot mode, with reference clock at 250 MHz, data rate at 3.125 GBs, and lane setup 4-1x ports and DSP System PLL at 100 MHz.
 |
 
-|  6. This will set the board to boot from Ethernet boot mode, with SerDes clock multiplier x 4, core PLL clock at 100 MHz.
+|  6. This will set the board to boot from Ethernet boot mode, with SerDes clock multiplier x 4, core PLL clock at 100 MHz.
 |
 
 |  7. This will set the board to boot form PCIE boot mode, with PCIE in end point mode and DSP System PLL at 100 MHz.

source/common/EVM_Hardware_Setup/_TMDXEVM6670L_EVM_Hardware_Setup.rst

@@ -71,7 +71,7 @@ Boot Mode Dip Switch Settings
 -----------------------------
 
 The EVM supports booting image from various devices (EEPROM, NAND or
-NOR) via IBL, it also supports ROM Boot modes, such as Ethernet, SRIO,
+NOR) via IBL, it also supports ROM Boot modes, such as Ethernet, SRIO,
 PCIe, etc. Below is the table showing the boot mode dip switch settings
 for different boot mode that the EVM supports:
 
@@ -120,16 +120,16 @@ for different boot mode that the EVM supports:
 
 **Footnotes:**
 
-| 1. Pin 1 of SW3 is the endian pin, by default, it is set to off (Little Endian)
+| 1. Pin 1 of SW3 is the endian pin, by default, it is set to off (Little Endian)
 |
 
-| 2. Pin 2-4 of SW3 are the boot mode pins, by default it is set to I2C boot mode (off, on, off)
+| 2. Pin 2-4 of SW3 are the boot mode pins, by default it is set to I2C boot mode (off, on, off)
 |
 
 | 3. Pin 1-4 of SW4 and pin 1-2 of SW5 are the boot parameter index pins for I2C boot (paramter index 0/1 for NOR boot image 0/1, parameter index 2/3 for NAND boot image 0/1, parameter index 4 for TFTP boot). By default, image 0 is programmed to offset byte address 0x0 on NOR, and 0x4000 (block 1 start address) on NAND, image 1 is programmed to offset byte address 0xA00000 on NOR, and 0x2000000 on NAND.
 |
 
-| 4. Pin 4 of SW5 is the I2C address pin (off: 0x51, on: 0x50)  for I2C boot mode
+| 4. Pin 4 of SW5 is the I2C address pin (off: 0x51, on: 0x50)  for I2C boot mode
 |
 
 | 5. This will set the board to boot from SRIO boot mode, with reference clock at 250 MHz, data rate at 3.125 GBs, and lane setup 4-1x ports and DSP System PLL at 122.88 MHz.

source/common/EVM_Hardware_Setup/_TMDXEVM6678L_EVM_Hardware_Setup.rst

@@ -74,7 +74,7 @@ The application needs an IP address. It can use either a static IP
 address (pre-configured) or it can request one using DHCP. This is
 controlled by setting dip switch 2 of SW9.
 
-| User Switch 2 ON : DHCP
+| User Switch 2 ON : DHCP
 | User Switch 2 OFF: Static IP
 
 .. image:: /images/TMD6678LSW9.png
@@ -110,7 +110,7 @@ Boot Mode Dip Switch Settings
 
 The EVM supports booting image from various devices (EEPROM, NAND or
 NOR) via IBL (at I2C address 0x51), I2C EEPROM (at I2C address 0x50),
-and ROM Boot modes (such as Ethernet, SRIO, PCIe, SPI etc.) which
+and ROM Boot modes (such as Ethernet, SRIO, PCIe, SPI etc.) which
 address the boot source directly from the ROM code. Below is the table
 showing the boot mode dip switch settings for different boot mode that
 the EVM supports:
@@ -121,7 +121,7 @@ the EVM supports:
 |                | (Pin1, 2, 3,   | (Pin1, 2, 3,   | (Pin1, 2, 3,   | (Pin1, 2, 3,   |
 |                | 4)             | 4)             | 4)             | 4)             |
 +================+================+================+================+================+
-| IBL NOR boot   | (off, off, on, | (on, on, on,   | (on, on, on,   | (on, on, on,   |
+| IBL NOR boot   | (off, off, on, | (on, on, on,   | (on, on, on,   | (on, on, on,   |
 | on image 0     | off)\ :sup:`1, | on)\ :sup:`3`  | off)\ :sup:`4` | on)            |
 | (default)      | 2`             |                |                |                |
 +----------------+----------------+----------------+----------------+----------------+
@@ -160,10 +160,10 @@ the EVM supports:
 
 | **Footnotes:**
 
-1. Pin 1 of SW3 is the endian pin, by default, it is set to off (Little
-Endian) 
+1. Pin 1 of SW3 is the endian pin, by default, it is set to off (Little
+Endian)
 
-2. Pin 2-4 of SW3 are the boot mode pins, by default it is set to I2C
+2. Pin 2-4 of SW3 are the boot mode pins, by default it is set to I2C
 boot mode (off, on, off)
 
 3. Pin 1-4 of SW4 and pin 1-2 of SW5 are the boot parameter index pins
@@ -173,15 +173,15 @@ default, image 0 is programmed to offset byte address 0x0 on NOR, and
 0x4000 (block 1 start address) on NAND, image 1 is programmed to offset
 byte address 0xA00000 on NOR, and 0x2000000 on NAND.
 
-4. Pin 4 of SW5 is the I2C address pin (off: 0x51, on: 0x50)  for I2C
+4. Pin 4 of SW5 is the I2C address pin (off: 0x51, on: 0x50)  for I2C
 boot mode
 
 5. This will set the board to boot from SRIO boot mode, with reference
 clock at 312.5 MHz, data rate at 3.125 GBs, and lane setup 4-1x ports
 and DSP System PLL at 100 MHz.
 
 6. This will set the board to boot from Ethernet boot mode, with SerDes
-clock multiplier x 4, core PLL clock at 100 MHz.
+clock multiplier x 4, core PLL clock at 100 MHz.
 
 7. This will set the board to boot form PCIE boot mode, with PCIE in end
 point mode and DSP System PLL at 100 MHz.

source/common/EVM_Hardware_Setup/_TMDXIDK5728_Hardware_Setup.rst

@@ -183,7 +183,7 @@ corresponding to FTDI UARTtoUSB will be turned on.
 .. rubric:: Connecting IDK EVM to Code Composer Studio
    :name: connecting-idk-evm-to-code-composer-studio
 
-**Step1 :** Download Code composer Studio and AM572x Sitara CSP package
+**Step1 :** Download Code composer Studio and AM572x Sitara CSP package
 as described in the wiki article mentioned below:
 
 `Install Code composer Studio for
@@ -285,11 +285,11 @@ is installed
     CortexA15_0: GEL Output: DEBUG: EMIF1 channel - Launch full levelling
     CortexA15_0: GEL Output: DEBUG: Setting LISA maps in non-interleaved dual-EMIF mode
     CortexA15_0: GEL Output: --->>> DDR3 Initialization is DONE! <<<---
-    CortexA15_0: GEL Output: --->>> AM572x Target Connect Sequence DONE !!!!!  <<<
+    CortexA15_0: GEL Output: --->>> AM572x Target Connect Sequence DONE !!!!!  <<<
 
 |
 
-**Step6** : To connect to the DSP, M4,PRUSS or to IVAHD go to Scripts
+**Step6** : To connect to the DSP, M4,PRUSS or to IVAHD go to Scripts
 menu and under AM572x MULTICORE Initialization enable the corresponding
 Sub system clock Enable API.For Eg. FOr DSP1 select
 DSP11SSClkEnable\_API. After running the clock enable option, you can

source/common/Industrial_Protocols/HSR_PRP/_Firmware.rst

@@ -216,7 +216,7 @@ Table:  **Shared RAM Memory Map**
 
 +--------------------------+--------------------------+--------------------------+
 | Name of Offset           | Description              | Offset in Shared RAM     |
-|                          | Refer to                 | (base : 0x140)           |
+|                          | Refer to                 | (base : 0x140)           |
 |                          | *hsr\_prp\_firmware.h*   |                          |
 +==========================+==========================+==========================+
 | LRE\_CNT\_TX\_A          | Number of frames         | *4*                      |

source/common/Industrial_Protocols/HSR_PRP/_Firmware_Features.rst

@@ -44,11 +44,11 @@ Firmware Features Supported
    -  Duplicate discard table on Port to Port path (HSR)
    -  Data integrity (CRC) check during port to port forwarding, except cut through (HSR)
 
--  **QoS scheme** : 3-bit VLAN PCP
+-  **QoS scheme** : 3-bit VLAN PCP
 
-   -  No of levels supported : 8
-   -  Number of host queues : 2 \| 4 QoS levels per host queue
-   -  Number of port queues : 4 \| 2 QoS levels per port queue
+   -  No of levels supported : 8
+   -  Number of host queues : 2 \| 4 QoS levels per host queue
+   -  Number of port queues : 4 \| 2 QoS levels per port queue
    -  Number of host queues are configurable
 
 -  **Statistics**
@@ -66,4 +66,4 @@ Firmware Features Supported
    -  Single and Two step clock supported
    -  Peer delay Response is always sent as two-step
 
--  **Storm Prevention** : Yes. Configurable per port
+-  **Storm Prevention** : Yes. Configurable per port

source/common/PRU-ICSS/Header_Files.rst

@@ -46,7 +46,7 @@ layout is like this:
 union{
 u32 register_name;
 struct {
-bit_field_names : bit_size;
+bit_field_names : bit_size;
 . . .
 } register_name_bit;
 };