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lines changed Original file line number Diff line number Diff line change @@ -21,7 +21,7 @@ if {[env_var_exists_and_non_empty SYNTH_HIER_SEPARATOR]} {
2121 scratchpad -set flatten.separator $::env(SYNTH_HIER_SEPARATOR)
2222}
2323
24- set synth_full_args $::env( SYNTH_ARGS)
24+ set synth_full_args [env_var_or_empty SYNTH_ARGS]
2525if {[env_var_exists_and_non_empty SYNTH_OPERATIONS_ARGS]} {
2626 set synth_full_args [concat $synth_full_args $::env(SYNTH_OPERATIONS_ARGS) ]
2727} else {
Original file line number Diff line number Diff line change 11source $::env(SCRIPTS_DIR) /synth_preamble.tcl
22read_design_sources
33
4- dict for {key value} $::env( VERILOG_TOP_PARAMS) {
4+ dict for {key value} [env_var_or_empty VERILOG_TOP_PARAMS] {
55 # Apply toplevel parameters
66 chparam -set $key $value $::env(DESIGN_NAME)
77}
Original file line number Diff line number Diff line change @@ -48,20 +48,22 @@ proc read_design_sources {} {
4848 plugin -i slang
4949 yosys read_slang -D SYNTHESIS --keep-hierarchy --compat=vcs \
5050 --ignore-assertions --top $::env(DESIGN_NAME) \
51- {*}$vIdirsArgs {*}$::env(VERILOG_FILES) {*}$::env( VERILOG_DEFINES)
51+ {*}$vIdirsArgs {*}$::env(VERILOG_FILES) {*}[env_var_or_empty VERILOG_DEFINES]
5252 # Workaround for yosys-slang#119
5353 setattr -unset init
5454 } elseif {[env_var_equals SYNTH_HDL_FRONTEND verific]} {
5555 if {[env_var_exists_and_non_empty VERILOG_INCLUDE_DIRS]} {
56- verific -vlog-incdir {*}$::env(VERILOG_INCLUDE_DIRS)
56+ verific -vlog-incdir {*}$::env(VERILOG_INCLUDE_DIRS)
5757 }
5858 if {[env_var_exists_and_non_empty VERILOG_DEFINES]} {
59- verific -vlog-define {*}$::env(VERILOG_DEFINES)
59+ verific -vlog-define {*}$::env(VERILOG_DEFINES)
6060 }
6161 verific -sv2012 {*}$::env(VERILOG_FILES)
6262 } elseif {![env_var_exists_and_non_empty SYNTH_HDL_FRONTEND]} {
6363 verilog_defaults -push
64- verilog_defaults -add {*}$::env(VERILOG_DEFINES)
64+ if {[env_var_exists_and_non_empty VERILOG_DEFINES]} {
65+ verilog_defaults -add {*}$::env(VERILOG_DEFINES)
66+ }
6567 foreach file $::env(VERILOG_FILES) {
6668 read_verilog -defer -sv {*}$vIdirsArgs $file
6769 }
Original file line number Diff line number Diff line change @@ -124,6 +124,14 @@ proc append_env_var {list_name var_name prefix has_arg} {
124124 }
125125}
126126
127+ # Non-empty defaults should go into variables.yaml, generally
128+ proc env_var_or_empty {env_var} {
129+ if {[env_var_exists_and_non_empty $env_var ]} {
130+ return $::env($env_var)
131+ }
132+ return " "
133+ }
134+
127135proc find_macros {} {
128136 set macros " "
129137
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