Merge pull request #1346 from Pinata-Consulting/mock-array-cleanup

mock-array: cleanup

Author: maliberty

flow/designs/asap7/mock-array/config.mk

@@ -34,8 +34,6 @@ export IO_CONSTRAINTS        = designs/asap7/mock-array/io.tcl
 
 export PDN_TCL               = designs/asap7/mock-array/pdn.tcl
 
-export TNS_END_PERCENT       = 100
-
 # Target to force generation of Verilog per user settings MOCK_ARRAY_TABLE (rows, cols)
 verilog:
 	export MOCK_ARRAY_ROWS=$(word 1, $(MOCK_ARRAY_TABLE)) ; \

flow/designs/asap7/mock-array/verilog.sh

@@ -12,5 +12,5 @@ cd ../../src/mock-array
 sbt -Duser.home="$HOME" -Djline.terminal=jline.UnsupportedTerminal -batch \
      "test:runMain GenerateMockArray --width ${MOCK_ARRAY_ROWS} --height ${MOCK_ARRAY_COLS} --dataWidth ${MOCK_ARRAY_DATAWIDTH} -- --emit-modules verilog --emission-options disableMemRandomization,disableRegisterRandomization --target-dir ."
 
-# reduce git noise as these comments will change if the line numbers in MockArray.scala changes
+# reduce git noise as these comments will change if the line numbers in Chisel changes
 find . -name "*.v" -type f -exec sed -i 's/ \/\/.*$//' {} \;

flow/designs/src/mock-array/.gitignore

@@ -1,5 +1,5 @@
-MockArray.anno.json
-MockArray.fir
+*.anno.json
+*.fir
 project/
 target/
 .metals/