Merge branch 'master' into mb@update

Signed-off-by: louiic <[email protected]>

Author: louiic

docs/user/FlowVariables.md

@@ -35,14 +35,12 @@ public platforms supported by the OpenROAD flow.
 Note:
 -   = indicates default definition assigned by the tool
 -   ?= indicates that the variable value may be reassigned with design `config.mk`
--   N/A indicates that the variable/files is not supported currently.
 
 
 | **Configuration Variable**           | **sky130hd** | **sky130hs** | **nangate45** | **asap7** | **gf180** |
 |--------------------------------------|--------------|--------------|---------------|-----------|-----------|
 | Library Setup                        |              |              |               |           |           |
 | `PROCESS`                            | =            | =            | =             | =         | =         |
-| `CORNER`                             | N/A          | N/A          | N/A           | ?=        | ?=        |
 | `TECH_LEF`                           | =            | =            | =             | =         | =         |
 | `SC_LEF`                             | =            | =            | =             | =         | =         |
 | `LIB_FILES`                          | =            | =            | =             | =         | =         |
@@ -62,8 +60,6 @@ Note:
 | `PLACE_SITE`                         | =            | =            | =             | =         | =         |
 | `MAKE_TRACKS`                        | =            | =            | =             | =         | =         |
 | `TAPCELL_TCL`                        | =            | =            | =             | =         | =         |
-| `MACRO_HALO_X`                       | NA           | NA           | NA            | ?=        | NA        |
-| `MACRO_HALO_Y`                       | NA           | NA           | NA            | ?=        | NA        |
 | `MACRO_PLACE_HALO`                   | ?=           | ?=           | ?=            | ?=        | ?=        |
 | `MACRO_PLACE_CHANNEL`                | ?=           | ?=           | ?=            | ?=        | ?=        |
 | `PDN_TCL`                            | ?=           | ?=           | ?=            | ?=        | ?=        |
@@ -82,8 +78,6 @@ Note:
 | `SKIP_PIN_SWAP`                      | ?=           | ?=           | ?=            | ?=        | ?=        |
 | `TNS_END_PERCENT`                    | ?=           | ?=           |               | ?=        | ?=        |
 | Routing                              |              |              |               |           |           |
-| `FASTROUTE_TCL`                      | ?=           | ?=           | ?=            | N/A       | N/A       |
-| `FILL_CONFIG`                        | =            | =            | N/A           | N/A       | N/A       |
 | `KLAYOUT_TECH_FILE`                  | =            | =            | =             | =         | =         |
 | `MAX_ROUTING_LAYER`                  | =            | =            | =             | =         | ?=        |
 | `MIN_ROUTING_LAYER`                  | =            | =            | =             | =         | ?=        |
@@ -120,6 +114,7 @@ Note:
 | `ABC_CLOCK_PERIOD_IN_PS` | Clock period to be used by STA during synthesis. Default value read from `constraint.sdc`. |
 | `ABC_DRIVER_CELL`        | Default driver cell used during ABC synthesis.                                             |
 | `ABC_LOAD_IN_FF`         | During synthesis set_load value used.                                                      |
+| `MAX_UNGROUP_SIZE`       | For hierarchical synthesis, we ungroup modules of size given by this variable.             |
 
 
 ### Floorplan
@@ -164,7 +159,7 @@ Note:
 | `SLEW_MARGIN`                        | Specifies a slew margin when fixing max slew violations. This option allow you to overfix.                                                    |
 
 
-### Clock Tree Synthesis(CTS)
+### Clock Tree Synthesis (CTS)
 
 
 | Variable              | Description                                                                                                  |
@@ -238,12 +233,18 @@ configuration file.
 | `ADDITIONAL_LIBS`        | Hardened macro library files listed here.                                                          |
 | `ADDITIONAL_GDS`         | Hardened macro GDS files listed here.                                                              |
 | `VERILOG_INCLUDE_DIRS`   | Specifies the include directories for the Verilog input files.                                     |
-| `CORNER`                 | PVT corner library selection.                                                                      |
+| `CORNER`                 | PVT corner library selection. Only available for ASAP7 and GF180 PDK.                                                                 |
 | `DESIGN_NICKNAME`        | DESIGN_NICKNAME just changes the directory name that ORFS outputs to be DESIGN_NICKNAME instead of DESIGN_NAME in case DESIGN_NAME is unwieldy or conflicts with a difference design.                                                                                    |
 | `ABC_AREA`               | Strategies for Yosys ABC synthesis: Area/Speed. Default ABC_SPEED.                                 |
 | `PWR_NETS_VOLTAGES`      | Used for IR Drop calculation.                                                                      |
 | `GND_NETS_VOLTAGES`      | Used for IR Drop calculation.                                                                      |
-
+| `BLOCKS`                 | Blocks used as hard macros in a hierarchical flow. Do note that you have to specify block-specific inputs file in the directory mentioned by [Makefile](../main/flow/Makefile) |
+| `CDL_FILES`              | Insert additional Circuit Description Language (`.cdl`) netlist files.                             | 
+| `DFF_LIB_FILES`          | Technology mapping liberty files for flip-flops.                                                   |
+| `DONT_USE_LIBS`          | Set liberty files as `dont_use`.                                                                   |
+| `PRESERVE_CELLS`         | Mark modules to keep from getting removed in flattening.                                           |
+| `SYNTH_ARGS`             | Optional synthesis variables for yosys.                                                            |
+| `VERILOG_TOP_PARAMS`     | Apply toplevel params (if exist).                                                                  |
 
 #### Floorplan
 
@@ -255,4 +256,33 @@ configuration file.
 | `CORE_MARGIN`         | The margin between the core area and die area, in multiples of SITE heights. The margin is applied to each side. This variable is ignored if `CORE_UTILIZATION` is undefined.                                                              |
 | `DIE_AREA`            | The die area specified as a list of lower-left and upper-right corners in microns (X1 Y1 X2 Y2). This variable is ignored if `CORE_UTILIZATION` and `CORE_ASPECT_RATIO` are defined.                                                       |
 | `CORE_AREA`           | The core area specified as a list of lower-left and upper-right corners in microns (X1 Y1 X2 Y2). This variable is ignored if `CORE_UTILIZATION` and `CORE_ASPECT_RATIO` are defined.                                                      |
+| `RESYNTH_AREA_RECOVER` | Enable re-synthesis for area reclaim. |
+| `RESYNTH_TIMING_RECOVER` | Enable re-synthesis for timing optimization. | 
+| `MACRO_HALO_X`         | Set macro halo for x-direction. Only available for ASAP7 PDK. |
+| `MACRO_HALO_Y`         | Set macro halo for y-direction. Only available for ASAP7 PDK. |
+
+## Placement
+
+
+| Variable                 | Description                                                                                        |
+|--------------------------|----------------------------------------------------------------------------------------------------|
+| `MACRO_WRAPPERS`         | The wrapper file that replace existing macros with their wrapped version.                          |
+
+
+## Clock Tree Synthesis
+
+
+| Variable                 | Description                                                                                        |
+|--------------------------|----------------------------------------------------------------------------------------------------|
+| `CTS_BUF_DISTANCE`       | Distance (in microns) between buffers.                                                              |
+| `CTS_CLUSTER_DIAMETER`   | Maximum diameter (in microns) of sink cluster. Default 20.                                         |
+| `CTS_CLUSTER_SIZE`       | Maximum number of sinks per cluster. Default 50.
+
+
+## Routing
+
+
+| Variable                 | Description                                                                                        |
+|--------------------------|----------------------------------------------------------------------------------------------------|
+| `FASTROUTE_TCL`          | Specifies a Tcl scripts with commands to run before FastRoute.                                      |
 

flow/designs/asap7/ibex/config.mk

@@ -15,3 +15,4 @@ export ENABLE_DPO = 0
 
 export DFF_LIB_FILE           = $($(CORNER)_DFF_LIB_FILE)
 export TNS_END_PERCENT        = 100
+

flow/designs/asap7/mock-alu/config.mk

@@ -9,8 +9,8 @@ export SDC_FILE               = designs/asap7/mock-alu/constraints.sdc
 
 export PLATFORM               = asap7
 
-export PLACE_DENSITY          = 0.60
-export CORE_UTILIZATION       = 40
+export PLACE_DENSITY          = 0.75
+export CORE_UTILIZATION       = 50
 export CORE_ASPECT_RATIO      = 1
 export CORE_MARGIN            = 2
 

flow/designs/asap7/mock-alu/constraints.sdc

@@ -1,6 +1,6 @@
 set clk_name clock
 set clk_port_name clock
-set clk_period 500
+set clk_period 750
 set clk_io_pct 0.2
 
 set clk_port [get_ports $clk_port_name]