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povikpovik
committed
Merge branch 'master' into secure-rsz-fully-rebuffer
2 parents ffd0da7 + 4c4bee1 commit 284adfc

27 files changed

+24188
-158
lines changed

‎flow/Makefile‎

Lines changed: 19 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -89,23 +89,29 @@ include $(DESIGN_CONFIG)
8989

9090
export DESIGN_DIR ?= $(dir $(DESIGN_CONFIG))
9191

92-
# default value "base" is duplicated from variables.yaml because we need it
92+
# default value "base" for FLOW_VARIANT and "." for WORK_HOME are duplicated
93+
# from variables.yaml and variables.mk because we need it
9394
# earlier in the flow for BLOCKS. BLOCKS is a feature specific to the
9495
# ORFS Makefile.
9596
export FLOW_VARIANT?=base
97+
export WORK_HOME?=.
9698
# BLOCKS is a ORFS make flow specific feature.
9799
ifneq ($(BLOCKS),)
98100
# Normally this comes from variables.yaml, but we need it here to set up these variables
99101
# which are part of the DESIGN_CONFIG. BLOCKS is a Makefile specific concept.
100-
$(foreach block,$(BLOCKS),$(eval BLOCK_LEFS += ./results/$(PLATFORM)/$(DESIGN_NICKNAME)_$(block)/$(FLOW_VARIANT)/${block}.lef))
101-
$(foreach block,$(BLOCKS),$(eval BLOCK_LIBS += ./results/$(PLATFORM)/$(DESIGN_NICKNAME)_$(block)/$(FLOW_VARIANT)/${block}.lib))
102-
$(foreach block,$(BLOCKS),$(eval BLOCK_GDS += ./results/$(PLATFORM)/$(DESIGN_NICKNAME)_$(block)/$(FLOW_VARIANT)/6_final.gds))
103-
$(foreach block,$(BLOCKS),$(eval BLOCK_CDL += ./results/$(PLATFORM)/$(DESIGN_NICKNAME)_$(block)/$(FLOW_VARIANT)/6_final.cdl))
104-
$(foreach block,$(BLOCKS),$(eval BLOCK_LOG_FOLDERS += ./logs/$(PLATFORM)/$(DESIGN_NICKNAME)_$(block)/$(FLOW_VARIANT)/))
102+
$(foreach block,$(BLOCKS),$(eval BLOCK_LEFS += $(WORK_HOME)/results/$(PLATFORM)/$(DESIGN_NICKNAME)_$(block)/$(FLOW_VARIANT)/${block}.lef))
103+
$(foreach block,$(BLOCKS),$(eval BLOCK_TYP_LIBS += $(WORK_HOME)/results/$(PLATFORM)/$(DESIGN_NICKNAME)_$(block)/$(FLOW_VARIANT)/${block}_typ.lib))
104+
$(foreach block,$(BLOCKS),$(eval BLOCK_FAST_LIBS += $(WORK_HOME)/results/$(PLATFORM)/$(DESIGN_NICKNAME)_$(block)/$(FLOW_VARIANT)/${block}_fast.lib))
105+
$(foreach block,$(BLOCKS),$(eval BLOCK_SLOW_LIBS += $(WORK_HOME)/results/$(PLATFORM)/$(DESIGN_NICKNAME)_$(block)/$(FLOW_VARIANT)/${block}_slow.lib))
106+
$(foreach block,$(BLOCKS),$(eval BLOCK_GDS += $(WORK_HOME)/results/$(PLATFORM)/$(DESIGN_NICKNAME)_$(block)/$(FLOW_VARIANT)/6_final.gds))
107+
$(foreach block,$(BLOCKS),$(eval BLOCK_CDL += $(WORK_HOME)/results/$(PLATFORM)/$(DESIGN_NICKNAME)_$(block)/$(FLOW_VARIANT)/6_final.cdl))
108+
$(foreach block,$(BLOCKS),$(eval BLOCK_LOG_FOLDERS += $(WORK_HOME)/logs/$(PLATFORM)/$(DESIGN_NICKNAME)_$(block)/$(FLOW_VARIANT)/))
105109
export ADDITIONAL_LEFS += $(BLOCK_LEFS)
106-
export ADDITIONAL_LIBS += $(BLOCK_LIBS)
110+
export ADDITIONAL_LIBS += $(BLOCK_TYP_LIBS)
111+
export ADDITIONAL_TYP_LIBS += $(BLOCK_TYP_LIBS)
112+
export ADDITIONAL_FAST_LIBS += $(BLOCK_FAST_LIBS)
113+
export ADDITIONAL_SLOW_LIBS += $(BLOCK_SLOW_LIBS)
107114
export ADDITIONAL_GDS += $(BLOCK_GDS)
108-
export GDS_FILES += $(BLOCK_GDS)
109115
ifneq ($(CDL_FILES),)
110116
export CDL_FILES += $(BLOCK_CDL)
111117
endif
@@ -140,7 +146,7 @@ SHELL := /usr/bin/env bash
140146
# location
141147
# - default is current install / clone directory
142148
ifeq ($(origin FLOW_HOME), undefined)
143-
FLOW_HOME := $(abspath $(dir $(firstword $(MAKEFILE_LIST))))
149+
FLOW_HOME := $(abspath $(dir $(firstword $(MAKEFILE_LIST))))
144150
endif
145151
export FLOW_HOME
146152

@@ -168,10 +174,10 @@ endef
168174

169175
# Targets to harden Blocks in case of hierarchical flow is triggered
170176
.PHONY: build_macros
171-
build_macros: $(BLOCK_LEFS) $(BLOCK_LIBS)
177+
build_macros: $(BLOCK_LEFS) $(BLOCK_TYP_LIBS)
172178

173-
$(foreach block,$(BLOCKS),$(eval $(call GENERATE_ABSTRACT_RULE,./results/$(PLATFORM)/$(DESIGN_NICKNAME)_$(block)/$(FLOW_VARIANT)/${block}.lef,./results/$(PLATFORM)/$(DESIGN_NICKNAME)_$(block)/$(FLOW_VARIANT)/${block}.lib,$(shell dirname $(DESIGN_CONFIG))/${block}/config.mk)))
174-
$(foreach block,$(BLOCKS),$(eval ./results/$(PLATFORM)/$(DESIGN_NICKNAME)_$(block)/$(FLOW_VARIANT)/6_final.gds: ./results/$(PLATFORM)/$(DESIGN_NICKNAME)_$(block)/$(FLOW_VARIANT)/${block}.lef))
179+
$(foreach block,$(BLOCKS),$(eval $(call GENERATE_ABSTRACT_RULE,$(WORK_HOME)/results/$(PLATFORM)/$(DESIGN_NICKNAME)_$(block)/$(FLOW_VARIANT)/${block}.lef,$(WORK_HOME)/results/$(PLATFORM)/$(DESIGN_NICKNAME)_$(block)/$(FLOW_VARIANT)/${block}_typ.lib,$(shell dirname $(DESIGN_CONFIG))/${block}/config.mk)))
180+
$(foreach block,$(BLOCKS),$(eval $(WORK_HOME)/results/$(PLATFORM)/$(DESIGN_NICKNAME)_$(block)/$(FLOW_VARIANT)/6_final.gds: $(WORK_HOME)/results/$(PLATFORM)/$(DESIGN_NICKNAME)_$(block)/$(FLOW_VARIANT)/${block}.lef))
175181

176182
# Utility to print tool version information
177183
#-------------------------------------------------------------------------------
@@ -765,7 +771,7 @@ clean_all: clean_synth clean_floorplan clean_place clean_cts clean_route clean_f
765771

766772
.PHONY: nuke
767773
nuke: clean_test clean_issues
768-
rm -rf ./results ./logs ./reports ./objects
774+
rm -rf $(WORK_HOME)/results $(WORK_HOME)/logs $(WORK_HOME)/reports $(WORK_HOME)/objects
769775
rm -rf layer_*.mps macrocell.list *best.plt *_pdn.def
770776
rm -rf *.rpt *.rpt.old *.def.v pin_dumper.log
771777
rm -f $(OBJECTS_DIR)/versions.txt $(OBJECTS_DIR)/copyright.txt dummy.guide

‎flow/designs/asap7/cva6/config.mk‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -79,10 +79,10 @@ export ADDITIONAL_LIBS = $(PLATFORM_DIR)/lib/NLDM/fakeram7_256x256.lib
7979

8080
export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc
8181

82-
export DIE_AREA = 0 0 350 350
83-
export CORE_AREA = 1.08 1.08 340 340
82+
export CORE_UTILIZATION = 40
83+
export CORE_MARGIN = 2
84+
export MACRO_HALO = 5
8485
export PLACE_DENSITY = 0.50
85-
export MACRO_HALO = 5 5
8686

8787
# a smoketest for this option, there are a
8888
# few last gasp iterations

‎flow/designs/asap7/cva6/rules-base.json‎

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
{
22
"synth__design__instance__area__stdcell": {
3-
"value": 40692.1,
3+
"value": 40631.65,
44
"compare": "<="
55
},
66
"constraints__clocks__count": {
@@ -12,27 +12,27 @@
1212
"compare": "<="
1313
},
1414
"placeopt__design__instance__count__stdcell": {
15-
"value": 164118,
15+
"value": 163049,
1616
"compare": "<="
1717
},
1818
"detailedplace__design__violations": {
1919
"value": 0,
2020
"compare": "=="
2121
},
2222
"cts__design__instance__count__setup_buffer": {
23-
"value": 14271,
23+
"value": 14178,
2424
"compare": "<="
2525
},
2626
"cts__design__instance__count__hold_buffer": {
27-
"value": 14271,
27+
"value": 14178,
2828
"compare": "<="
2929
},
3030
"globalroute__antenna_diodes_count": {
3131
"value": 0,
3232
"compare": "<="
3333
},
3434
"detailedroute__route__wirelength": {
35-
"value": 1618999,
35+
"value": 1884562,
3636
"compare": "<="
3737
},
3838
"detailedroute__route__drc_errors": {
@@ -56,15 +56,15 @@
5656
"compare": "<="
5757
},
5858
"finish__timing__drv__setup_violation_count": {
59-
"value": 7136,
59+
"value": 7089,
6060
"compare": "<="
6161
},
6262
"finish__timing__drv__hold_violation_count": {
63-
"value": 105,
63+
"value": 101,
6464
"compare": "<="
6565
},
6666
"finish__timing__wns_percent_delay": {
67-
"value": -20.43,
67+
"value": -20.3,
6868
"compare": ">="
6969
}
7070
}

‎flow/designs/asap7/jpeg_lvt/config.mk‎

Lines changed: 3 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -8,15 +8,6 @@ export VERILOG_INCLUDE_DIRS = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/include
88
export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/jpeg_encoder15_7nm.sdc
99
export ABC_AREA = 1
1010

11-
export ADDITIONAL_LIBS = $(LIB_DIR)/asap7sc7p5t_AO_LVT_FF_nldm_211120.lib.gz \
12-
$(LIB_DIR)/asap7sc7p5t_INVBUF_LVT_FF_nldm_220122.lib.gz \
13-
$(LIB_DIR)/asap7sc7p5t_OA_LVT_FF_nldm_211120.lib.gz \
14-
$(LIB_DIR)/asap7sc7p5t_SIMPLE_LVT_FF_nldm_211120.lib.gz \
15-
$(LIB_DIR)/asap7sc7p5t_SEQ_LVT_FF_nldm_220123.lib
16-
17-
export ADDITIONAL_GDS = $(PLATFORM_DIR)/gds/asap7sc7p5t_28_L_220121a.gds
18-
export ADDITIONAL_LEFS = $(PLATFORM_DIR)/lef/asap7sc7p5t_28_L_1x_220121a.lef
19-
2011
export CORE_UTILIZATION = 30
2112
export CORE_ASPECT_RATIO = 1
2213
export CORE_MARGIN = 2
@@ -25,3 +16,6 @@ export PLACE_DENSITY = 0.60
2516
export TNS_END_PERCENT = 100
2617
export RECOVER_POWER = 100
2718

19+
export ASAP7_USE_VT = LVT
20+
21+

‎flow/designs/ihp-sg13g2/ibex/rules-base.json‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -12,7 +12,7 @@
1212
"compare": "<="
1313
},
1414
"placeopt__design__instance__count__stdcell": {
15-
"value": 20844,
15+
"value": 21142,
1616
"compare": "<="
1717
},
1818
"detailedplace__design__violations": {
@@ -44,7 +44,7 @@
4444
"compare": "<="
4545
},
4646
"detailedroute__antenna_diodes_count": {
47-
"value": 51,
47+
"value": 32,
4848
"compare": "<="
4949
},
5050
"finish__timing__setup__ws": {

‎flow/designs/sky130hd/microwatt/rules-base.json‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -28,7 +28,7 @@
2828
"compare": "<="
2929
},
3030
"globalroute__antenna_diodes_count": {
31-
"value": 933,
31+
"value": 5426,
3232
"compare": "<="
3333
},
3434
"detailedroute__route__wirelength": {
@@ -40,7 +40,7 @@
4040
"compare": "<="
4141
},
4242
"detailedroute__antenna__violating__nets": {
43-
"value": 9,
43+
"value": 0,
4444
"compare": "<="
4545
},
4646
"detailedroute__antenna_diodes_count": {

‎flow/designs/sky130hs/ibex/rules-base.json‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -32,7 +32,7 @@
3232
"compare": "<="
3333
},
3434
"detailedroute__route__wirelength": {
35-
"value": 911447,
35+
"value": 908310,
3636
"compare": "<="
3737
},
3838
"detailedroute__route__drc_errors": {

‎flow/platforms/asap7/config.mk‎

Lines changed: 82 additions & 61 deletions
Original file line numberDiff line numberDiff line change
@@ -80,94 +80,114 @@ export KLAYOUT_DRC_FILE = $(PLATFORM_DIR)/drc/asap7.lydrc
8080
# OpenRCX extRules
8181
export RCX_RULES = $(PLATFORM_DIR)/rcx_patterns.rules
8282

83-
# XS - defining function for using LVT
84-
ifeq ($(ASAP7_USE_VT), LVT)
85-
export VT_TAG = L
86-
else ifeq ($(ASAP7_USE_VT), SLVT)
87-
export VT_TAG = SL
88-
else
89-
# Default to RVT
90-
export VT_TAG = R
91-
endif
92-
83+
# PLACEHOLDER gets replaced with the appropriate VT tag in the following templates
84+
export BC_NLDM_DFF_LIB_FILE_T = $(LIB_DIR)/asap7sc7p5t_SEQ_PLACEHOLDERVT_FF_nldm_220123.lib
85+
export BC_CCS_DFF_LIB_FILE_T = $(LIB_DIR)/asap7sc7p5t_SEQ_PLACEHOLDERVT_FF_ccs_220123.lib
86+
export WC_NLDM_DFF_LIB_FILE_T = $(LIB_DIR)/asap7sc7p5t_SEQ_PLACEHOLDERVT_SS_nldm_220123.lib
87+
export TC_NLDM_DFF_LIB_FILE_T = $(LIB_DIR)/asap7sc7p5t_SEQ_PLACEHOLDERVT_TT_nldm_220123.lib
88+
export BC_NLDM_LIB_FILES_T = $(LIB_DIR)/asap7sc7p5t_AO_PLACEHOLDERVT_FF_nldm_211120.lib.gz \
89+
$(LIB_DIR)/asap7sc7p5t_INVBUF_PLACEHOLDERVT_FF_nldm_220122.lib.gz \
90+
$(LIB_DIR)/asap7sc7p5t_OA_PLACEHOLDERVT_FF_nldm_211120.lib.gz \
91+
$(LIB_DIR)/asap7sc7p5t_SIMPLE_PLACEHOLDERVT_FF_nldm_211120.lib.gz \
92+
$(LIB_DIR)/asap7sc7p5t_SEQ_PLACEHOLDERVT_FF_nldm_220123.lib
93+
export BC_CCS_LIB_FILES_T = $(LIB_DIR)/asap7sc7p5t_AO_PLACEHOLDERVT_FF_ccs_211120.lib.gz \
94+
$(LIB_DIR)/asap7sc7p5t_INVBUF_PLACEHOLDERVT_FF_ccs_220122.lib.gz \
95+
$(LIB_DIR)/asap7sc7p5t_OA_PLACEHOLDERVT_FF_ccs_211120.lib.gz \
96+
$(LIB_DIR)/asap7sc7p5t_SIMPLE_PLACEHOLDERVT_FF_ccs_211120.lib.gz \
97+
$(LIB_DIR)/asap7sc7p5t_SEQ_PLACEHOLDERVT_FF_ccs_220123.lib
98+
export WC_NLDM_LIB_FILES_T = $(LIB_DIR)/asap7sc7p5t_AO_PLACEHOLDERVT_SS_nldm_211120.lib.gz \
99+
$(LIB_DIR)/asap7sc7p5t_INVBUF_PLACEHOLDERVT_SS_nldm_220122.lib.gz \
100+
$(LIB_DIR)/asap7sc7p5t_OA_PLACEHOLDERVT_SS_nldm_211120.lib.gz \
101+
$(LIB_DIR)/asap7sc7p5t_SEQ_PLACEHOLDERVT_SS_nldm_220123.lib \
102+
$(LIB_DIR)/asap7sc7p5t_SIMPLE_PLACEHOLDERVT_SS_nldm_211120.lib.gz
103+
export TC_NLDM_LIB_FILES_T = $(LIB_DIR)/asap7sc7p5t_AO_PLACEHOLDERVT_TT_nldm_211120.lib.gz \
104+
$(LIB_DIR)/asap7sc7p5t_INVBUF_PLACEHOLDERVT_TT_nldm_220122.lib.gz \
105+
$(LIB_DIR)/asap7sc7p5t_OA_PLACEHOLDERVT_TT_nldm_211120.lib.gz \
106+
$(LIB_DIR)/asap7sc7p5t_SEQ_PLACEHOLDERVT_TT_nldm_220123.lib \
107+
$(LIB_DIR)/asap7sc7p5t_SIMPLE_PLACEHOLDERVT_TT_nldm_211120.lib.gz
108+
export FILL_CELLS_T = FILLERxp5_ASAP7_75t_ \
109+
FILLER_ASAP7_75t_ \
110+
DECAPx1_ASAP7_75t_ \
111+
DECAPx2_ASAP7_75t_ \
112+
DECAPx4_ASAP7_75t_ \
113+
DECAPx6_ASAP7_75t_ \
114+
DECAPx10_ASAP7_75t_
115+
116+
# Default to RVT if unset
117+
export VT_LIST = $(if $(strip $(ASAP7_USE_VT)), $(ASAP7_USE_VT), RVT)
118+
119+
# # The first VT in the ASAP7_USE_VT list is the primary VT. The others get added to OTHER_VT
120+
export PRIMARY_VT = $(word 1, $(VT_LIST))
121+
export PRIMARY_VT_TAG = $(strip $(patsubst %VT, %, $(PRIMARY_VT)))
122+
export OTHER_VT = $(wordlist 2, $(words $(VT_LIST)), $(VT_LIST))
123+
124+
## Set cells based on the primary VT first
93125
# Set the TIEHI/TIELO cells
94126
# These are used in yosys synthesis to avoid logical 1/0's in the netlist
95-
export TIEHI_CELL_AND_PORT ?= TIEHIx1_ASAP7_75t_$(VT_TAG) H
96-
export TIELO_CELL_AND_PORT ?= TIELOx1_ASAP7_75t_$(VT_TAG) L
127+
export TIEHI_CELL_AND_PORT ?= TIEHIx1_ASAP7_75t_$(PRIMARY_VT_TAG) H
128+
export TIELO_CELL_AND_PORT ?= TIELOx1_ASAP7_75t_$(PRIMARY_VT_TAG) L
97129

98130
# Used in synthesis
99-
export MIN_BUF_CELL_AND_PORTS ?= BUFx2_ASAP7_75t_$(VT_TAG) A Y
131+
export MIN_BUF_CELL_AND_PORTS ?= BUFx2_ASAP7_75t_$(PRIMARY_VT_TAG) A Y
100132

101-
export HOLD_BUF_CELL ?= BUFx2_ASAP7_75t_$(VT_TAG)
133+
export HOLD_BUF_CELL ?= BUFx2_ASAP7_75t_$(PRIMARY_VT_TAG)
102134

103-
export ABC_DRIVER_CELL ?= BUFx2_ASAP7_75t_$(VT_TAG)
135+
export ABC_DRIVER_CELL ?= BUFx2_ASAP7_75t_$(PRIMARY_VT_TAG)
104136

105137
# Fill cells used in fill cell insertion
106-
export FILL_CELLS ?= FILLERxp5_ASAP7_75t_$(VT_TAG) \
107-
FILLER_ASAP7_75t_$(VT_TAG) \
108-
DECAPx1_ASAP7_75t_$(VT_TAG) \
109-
DECAPx2_ASAP7_75t_$(VT_TAG) \
110-
DECAPx4_ASAP7_75t_$(VT_TAG) \
111-
DECAPx6_ASAP7_75t_$(VT_TAG) \
112-
DECAPx10_ASAP7_75t_$(VT_TAG)
138+
export FILL_CELLS ?= $(addsuffix $(PRIMARY_VT_TAG), $(FILL_CELLS_T))
113139

114-
export TAP_CELL_NAME ?= TAPCELL_ASAP7_75t_$(VT_TAG)
140+
export TAP_CELL_NAME ?= TAPCELL_ASAP7_75t_$(PRIMARY_VT_TAG)
115141

116142
# GDS_FILES has to be = vs. ?= because GDS_FILES gets set in the ORFS Makefile
117-
export GDS_FILES = $(PLATFORM_DIR)/gds/asap7sc7p5t_28_$(VT_TAG)_220121a.gds \
118-
$(ADDITIONAL_GDS)
143+
export GDS_FILES = $(PLATFORM_DIR)/gds/asap7sc7p5t_28_$(PRIMARY_VT_TAG)_220121a.gds
119144

120-
export SC_LEF ?= $(PLATFORM_DIR)/lef/asap7sc7p5t_28_$(VT_TAG)_1x_220121a.lef
145+
export SC_LEF ?= $(PLATFORM_DIR)/lef/asap7sc7p5t_28_$(PRIMARY_VT_TAG)_1x_220121a.lef
121146

122147
# Yosys mapping files
123-
export LATCH_MAP_FILE ?= $(PLATFORM_DIR)/yoSys/cells_latch_$(VT_TAG).v
124-
export CLKGATE_MAP_FILE ?= $(PLATFORM_DIR)/yoSys/cells_clkgate_$(VT_TAG).v
125-
export ADDER_MAP_FILE ?= $(PLATFORM_DIR)/yoSys/cells_adders_$(VT_TAG).v
126-
127-
export BC_NLDM_DFF_LIB_FILE ?= $(LIB_DIR)/asap7sc7p5t_SEQ_$(VT_TAG)VT_FF_nldm_220123.lib
128-
129-
export BC_NLDM_LIB_FILES ?= $(LIB_DIR)/asap7sc7p5t_AO_$(VT_TAG)VT_FF_nldm_211120.lib.gz \
130-
$(LIB_DIR)/asap7sc7p5t_INVBUF_$(VT_TAG)VT_FF_nldm_220122.lib.gz \
131-
$(LIB_DIR)/asap7sc7p5t_OA_$(VT_TAG)VT_FF_nldm_211120.lib.gz \
132-
$(LIB_DIR)/asap7sc7p5t_SIMPLE_$(VT_TAG)VT_FF_nldm_211120.lib.gz \
133-
$(LIB_DIR)/asap7sc7p5t_SEQ_$(VT_TAG)VT_FF_nldm_220123.lib
134-
135-
export BC_CCS_LIB_FILES ?= $(LIB_DIR)/asap7sc7p5t_AO_$(VT_TAG)VT_FF_ccs_211120.lib.gz \
136-
$(LIB_DIR)/asap7sc7p5t_INVBUF_$(VT_TAG)VT_FF_ccs_220122.lib.gz \
137-
$(LIB_DIR)/asap7sc7p5t_OA_$(VT_TAG)VT_FF_ccs_211120.lib.gz \
138-
$(LIB_DIR)/asap7sc7p5t_SIMPLE_$(VT_TAG)VT_FF_ccs_211120.lib.gz \
139-
$(LIB_DIR)/asap7sc7p5t_SEQ_$(VT_TAG)VT_FF_ccs_220123.lib \
140-
$(BC_ADDITIONAL_LIBS)
148+
export LATCH_MAP_FILE ?= $(PLATFORM_DIR)/yoSys/cells_latch_$(PRIMARY_VT_TAG).v
149+
export CLKGATE_MAP_FILE ?= $(PLATFORM_DIR)/yoSys/cells_clkgate_$(PRIMARY_VT_TAG).v
150+
export ADDER_MAP_FILE ?= $(PLATFORM_DIR)/yoSys/cells_adders_$(PRIMARY_VT_TAG).v
141151

142-
export BC_CCS_DFF_LIB_FILE ?= $(LIB_DIR)/asap7sc7p5t_SEQ_$(VT_TAG)VT_FF_ccs_220123.lib
143-
144-
export WC_NLDM_DFF_LIB_FILE ?= $(LIB_DIR)/asap7sc7p5t_SEQ_$(VT_TAG)VT_SS_nldm_220123.lib
145-
146-
export WC_NLDM_LIB_FILES ?= $(LIB_DIR)/asap7sc7p5t_AO_$(VT_TAG)VT_SS_nldm_211120.lib.gz \
147-
$(LIB_DIR)/asap7sc7p5t_INVBUF_$(VT_TAG)VT_SS_nldm_220122.lib.gz \
148-
$(LIB_DIR)/asap7sc7p5t_OA_$(VT_TAG)VT_SS_nldm_211120.lib.gz \
149-
$(LIB_DIR)/asap7sc7p5t_SEQ_$(VT_TAG)VT_SS_nldm_220123.lib \
150-
$(LIB_DIR)/asap7sc7p5t_SIMPLE_$(VT_TAG)VT_SS_nldm_211120.lib.gz
152+
export BC_NLDM_DFF_LIB_FILE ?= $(subst PLACEHOLDER,$(PRIMARY_VT_TAG),$(BC_NLDM_DFF_LIB_FILE_T))
153+
export BC_NLDM_LIB_FILES ?= $(subst PLACEHOLDER,$(PRIMARY_VT_TAG),$(BC_NLDM_LIB_FILES_T))
154+
export BC_CCS_LIB_FILES ?= $(subst PLACEHOLDER,$(PRIMARY_VT_TAG),$(BC_CCS_LIB_FILES_T)) \
155+
$(BC_ADDITIONAL_LIBS)
156+
export BC_CCS_DFF_LIB_FILE ?= $(subst PLACEHOLDER,$(PRIMARY_VT_TAG),$(BC_CCS_DFF_LIB_FILE_T))
151157

152-
export TC_NLDM_DFF_LIB_FILE ?= $(LIB_DIR)/asap7sc7p5t_SEQ_$(VT_TAG)VT_TT_nldm_220123.lib
158+
export WC_NLDM_DFF_LIB_FILE ?= $(subst PLACEHOLDER,$(PRIMARY_VT_TAG),$(WC_NLDM_DFF_LIB_FILE_T))
159+
export WC_NLDM_LIB_FILES ?= $(subst PLACEHOLDER,$(PRIMARY_VT_TAG),$(WC_NLDM_LIB_FILES_T))
153160

154-
export TC_NLDM_LIB_FILES ?= $(LIB_DIR)/asap7sc7p5t_AO_$(VT_TAG)VT_TT_nldm_211120.lib.gz \
155-
$(LIB_DIR)/asap7sc7p5t_INVBUF_$(VT_TAG)VT_TT_nldm_220122.lib.gz \
156-
$(LIB_DIR)/asap7sc7p5t_OA_$(VT_TAG)VT_TT_nldm_211120.lib.gz \
157-
$(LIB_DIR)/asap7sc7p5t_SEQ_$(VT_TAG)VT_TT_nldm_220123.lib \
158-
$(LIB_DIR)/asap7sc7p5t_SIMPLE_$(VT_TAG)VT_TT_nldm_211120.lib.gz
161+
export TC_NLDM_DFF_LIB_FILE ?= $(subst PLACEHOLDER,$(PRIMARY_VT_TAG),$(TC_NLDM_DFF_LIB_FILE_T))
162+
export TC_NLDM_LIB_FILES ?= $(subst PLACEHOLDER,$(PRIMARY_VT_TAG),$(TC_NLDM_LIB_FILES_T))
159163

160164
ifeq ($(CLUSTER_FLOPS),1)
161165
# Add the multi-bit FF for clustering. These are single corner libraries.
162-
export ADDITIONAL_LIBS += $(LIB_DIR)/asap7sc7p5t_DFFHQNH2V2X_$(VT_TAG)VT_TT_nldm_FAKE.lib \
163-
$(LIB_DIR)/asap7sc7p5t_DFFHQNV2X_$(VT_TAG)VT_TT_nldm_FAKE.lib
166+
export ADDITIONAL_LIBS += $(LIB_DIR)/asap7sc7p5t_DFFHQNH2V2X_$(PRIMARY_VT_TAG)VT_TT_nldm_FAKE.lib \
167+
$(LIB_DIR)/asap7sc7p5t_DFFHQNV2X_$(PRIMARY_VT_TAG)VT_TT_nldm_FAKE.lib
164168

165169
export ADDITIONAL_LEFS += $(PLATFORM_DIR)/lef/asap7sc7p5t_DFFHQNH2V2X.lef \
166170
$(PLATFORM_DIR)/lef/asap7sc7p5t_DFFHQNV2X.lef
167171
export ADDITIONAL_SITES += asap7sc7p5t_pg
168172
export GDS_ALLOW_EMPTY ?= DFFHQN[VH][24].*
169173
endif
170174

175+
### Add additional files to the variables based on the OTHER_VT list
176+
$(foreach vt_type,$(OTHER_VT),\
177+
$(eval OTHER_VT_TAG = $(strip $(patsubst %VT, %, $(vt_type)))) \
178+
$(eval ADDITIONAL_LEFS += $(PLATFORM_DIR)/lef/asap7sc7p5t_28_$(OTHER_VT_TAG)_1x_220121a.lef) \
179+
$(eval BC_NLDM_DFF_LIB_FILE += $(subst PLACEHOLDER,$(OTHER_VT_TAG),$(BC_NLDM_DFF_LIB_FILE_T))) \
180+
$(eval BC_CCS_DFF_LIB_FILE += $(subst PLACEHOLDER,$(OTHER_VT_TAG),$(BC_CCS_DFF_LIB_FILE_T))) \
181+
$(eval WC_NLDM_DFF_LIB_FILE += $(subst PLACEHOLDER,$(OTHER_VT_TAG),$(WC_NLDM_DFF_LIB_FILE_T))) \
182+
$(eval TC_NLDM_DFF_LIB_FILE += $(subst PLACEHOLDER,$(OTHER_VT_TAG),$(TC_NLDM_DFF_LIB_FILE_T))) \
183+
$(eval BC_NLDM_LIB_FILES += $(subst PLACEHOLDER,$(OTHER_VT_TAG),$(BC_NLDM_LIB_FILES_T))) \
184+
$(eval BC_CCS_LIB_FILES += $(subst PLACEHOLDER,$(OTHER_VT_TAG),$(BC_CCS_LIB_FILES_T))) \
185+
$(eval WC_NLDM_LIB_FILES += $(subst PLACEHOLDER,$(OTHER_VT_TAG),$(WC_NLDM_LIB_FILES_T))) \
186+
$(eval TC_NLDM_LIB_FILES += $(subst PLACEHOLDER,$(OTHER_VT_TAG),$(TC_NLDM_LIB_FILES_T))) \
187+
$(eval GDS_FILES += $(PLATFORM_DIR)/gds/asap7sc7p5t_28_$(OTHER_VT_TAG)_220121a.gds) \
188+
$(eval FILL_CELLS += $(addsuffix $(PRIMARY_VT_TAG), $(FILL_CELLS_T))) \
189+
)
190+
171191
# Dont use SC library based on CORNER selection
172192
#
173193
# BC - Best case, fastest
@@ -176,6 +196,7 @@ endif
176196
export CORNER ?= BC
177197
export LIB_FILES += $($(CORNER)_$(LIB_MODEL)_LIB_FILES)
178198
export LIB_FILES += $(ADDITIONAL_LIBS)
199+
export GDS_FILES += $(ADDITIONAL_GDS)
179200
export DB_FILES += $(realpath $($(CORNER)_DB_FILES))
180201
export TEMPERATURE = $($(CORNER)_TEMPERATURE)
181202
export VOLTAGE = $($(CORNER)_VOLTAGE)

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