Merge pull request #3319 from The-OpenROAD-Project-staging/synth-port-naming

maliberty · web-flow · commit 4a9b19fda62a · 2025-07-16T18:59:46.000Z
synth: Adjust verific port naming to match slang
diff --git a/flow/scripts/synth_preamble.tcl b/flow/scripts/synth_preamble.tcl
@@ -59,6 +59,7 @@ proc read_design_sources { } {
       verific -vlog-define {*}$::env(VERILOG_DEFINES)
     }
     verific -sv2012 {*}$::env(VERILOG_FILES)
+    verific -import -no-split-complex-ports $::env(DESIGN_NAME)
   } elseif { ![env_var_exists_and_non_empty SYNTH_HDL_FRONTEND] } {
     verilog_defaults -push
     if { [env_var_exists_and_non_empty VERILOG_DEFINES] } {

Original file line number	Diff line number	Diff line change
`@@ -59,6 +59,7 @@ proc read_design_sources { } {`
`59`	`59`	`verific -vlog-define {*}$::env(VERILOG_DEFINES)`
`60`	`60`	`}`
`61`	`61`	`verific -sv2012 {*}$::env(VERILOG_FILES)`
	`62`	`+ verific -import -no-split-complex-ports $::env(DESIGN_NAME)`
`62`	`63`	`} elseif { ![env_var_exists_and_non_empty SYNTH_HDL_FRONTEND] } {`
`63`	`64`	`verilog_defaults -push`
`64`	`65`	`if { [env_var_exists_and_non_empty VERILOG_DEFINES] } {`