Merge pull request #3076 from povik/synth-yosys-slang

Integrate yosys-slang

Author: maliberty

.gitmodules

@@ -4,3 +4,6 @@
 [submodule "tools/OpenROAD"]
 	path = tools/OpenROAD
 	url = ../OpenROAD.git
+[submodule "tools/yosys-slang"]
+	path = tools/yosys-slang
+	url = https://github.com/povik/yosys-slang.git

build_openroad.sh

@@ -21,7 +21,7 @@ OPENROAD_APP_BRANCH="master"
 INSTALL_PATH="$(pwd)/tools/install"
 
 YOSYS_USER_ARGS=""
-YOSYS_ARGS="CONFIG=clang"
+YOSYS_ARGS=""
 
 OPENROAD_APP_USER_ARGS=""
 OPENROAD_APP_ARGS=""
@@ -246,6 +246,9 @@ __local_build()
         echo "[INFO FLW-0017] Compiling Yosys."
         ${NICE} make install -C tools/yosys -j "${PROC}" ${YOSYS_ARGS}
 
+        echo "[INFO FLW-0030] Compiling yosys-slang."
+        ${NICE} make install -C tools/yosys-slang -j "${PROC}" YOSYS_PREFIX="${INSTALL_PATH}/yosys/bin/"
+
         echo "[INFO FLW-0018] Compiling OpenROAD."
         eval ${NICE} ./tools/OpenROAD/etc/Build.sh -dir="$DIR/tools/OpenROAD/build" -threads=${PROC} -cmake=\'${OPENROAD_APP_ARGS}\'
         ${NICE} cmake --build tools/OpenROAD/build --target install -j "${PROC}"
@@ -340,7 +343,7 @@ __common_setup
 
 # Choose install method
 if [ -z "${LOCAL_BUILD+x}" ] && command -v docker &> /dev/null; then
-        echo -n "[INFO FLW-0000] Using docker build method."
+        echo "[INFO FLW-0000] Using docker build method."
         __docker_build
 else
         echo -n "[INFO FLW-0001] Using local build method."

docs/tutorials/FlowTutorial.md

@@ -187,15 +187,15 @@ minimum required timing constraint.
 create_clock -name core_clock -period 17.4 [get_ports {clk_i}]
 ```
 
-### Design Input Verilog
+### Design Input SystemVerilog
 
-The Verilog input files are located in `./designs/src/ibex/`
+The SystemVerilog input files are located in `./designs/src/ibex_sv/`
 
-The design is defined in `ibex_core.v` available
-[here](https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/blob/master/flow/designs/src/ibex/ibex_core.v).
+The design is defined in `ibex_core.sv` available
+[here](https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/blob/master/flow/designs/src/ibex_sv/ibex_core.sv).
 
 Refer to the `ibex` design `README.md`
-[here](https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/blob/master/flow/designs/src/ibex/README.md).
+[here](https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/blob/master/flow/designs/src/ibex_sv/README.md).
 
 ## Running The Automated RTL-to-GDS Flow
 

docs/user/BuildLocally.md

@@ -32,6 +32,7 @@ up the environment. The `make` command runs from RTL-GDSII generation for defaul
 ``` shell
 source ./env.sh
 yosys -help
+yosys -m slang -p "slang_version"
 openroad -help
 cd flow
 make

docs/user/BuildWithDocker.md

@@ -79,6 +79,7 @@ Then, inside docker:
 ``` shell
 source ./env.sh
 yosys -help
+yosys -m slang -p "slang_version"
 openroad -help
 cd flow
 make

docs/user/BuildWithPrebuilt.md

@@ -63,6 +63,7 @@ export YOSYS_EXE=$(command -v yosys)
 export LD_LIBRARY_PATH="<klayout_location>/bin:$PATH"
 
 yosys -help
+yosys -m slang -p "slang_version"
 openroad -help
 cd flow
 make

docs/user/FlowVariables.md

@@ -183,6 +183,7 @@ configuration file.
 | <a name="SYNTH_ARGS"></a>SYNTH_ARGS| Optional synthesis variables for yosys.| -flatten| |
 | <a name="SYNTH_BLACKBOXES"></a>SYNTH_BLACKBOXES| List of cells treated as a black box by Yosys. With Bazel, this can be used to run synthesis in parallel for the large modules of the design.| | |
 | <a name="SYNTH_GUT"></a>SYNTH_GUT| Load design and remove all internal logic before doing synthesis. This is useful when creating a mock .lef abstract that has a smaller area than the amount of logic would allow. bazel-orfs uses this to mock SRAMs, for instance.| | |
+| <a name="SYNTH_HDL_FRONTEND"></a>SYNTH_HDL_FRONTEND| Select an alternative language frontend to ingest the design. Available option is "slang". If the variable is empty, design is read with the Yosys read_verilog command.| | |
 | <a name="SYNTH_HIERARCHICAL"></a>SYNTH_HIERARCHICAL| Enable to Synthesis hierarchically, otherwise considered flat synthesis.| 0| |
 | <a name="SYNTH_KEEP_MODULES"></a>SYNTH_KEEP_MODULES| Mark modules to keep from getting removed in flattening.| | |
 | <a name="SYNTH_MEMORY_MAX_BITS"></a>SYNTH_MEMORY_MAX_BITS| Maximum number of bits for memory synthesis.| 4096| |
@@ -196,7 +197,8 @@ configuration file.
 | <a name="TIELO_CELL_AND_PORT"></a>TIELO_CELL_AND_PORT| Tie low cells used in Yosys synthesis to replace a logical 0 in the Netlist.| | |
 | <a name="TNS_END_PERCENT"></a>TNS_END_PERCENT| Default TNS_END_PERCENT value for post CTS timing repair. Try fixing all violating endpoints by default (reduce to 5% for runtime). Specifies how many percent of violating paths to fix [0-100]. Worst path will always be fixed.| 100| |
 | <a name="USE_FILL"></a>USE_FILL| Whether to perform metal density filling.| 0| |
-| <a name="VERILOG_FILES"></a>VERILOG_FILES| The path to the design Verilog files or JSON files providing a description of modules (check `yosys -h write_json` for more details).| | |
+| <a name="VERILOG_DEFINES"></a>VERILOG_DEFINES| Preprocessor defines passed to the language frontend. Example: `-D HPDCACHE_ASSERT_OFF`| | |
+| <a name="VERILOG_FILES"></a>VERILOG_FILES| The path to the design Verilog/SystemVerilog files providing a description of modules.| | |
 | <a name="VERILOG_INCLUDE_DIRS"></a>VERILOG_INCLUDE_DIRS| Specifies the include directories for the Verilog input files.| | |
 | <a name="VERILOG_TOP_PARAMS"></a>VERILOG_TOP_PARAMS| Apply toplevel params (if exist).| | |
 | <a name="YOSYS_FLAGS"></a>YOSYS_FLAGS| Flags to pass to yosys.| -v 3| |
@@ -214,6 +216,7 @@ configuration file.
 - [SDC_GUT](#SDC_GUT)
 - [SYNTH_BLACKBOXES](#SYNTH_BLACKBOXES)
 - [SYNTH_GUT](#SYNTH_GUT)
+- [SYNTH_HDL_FRONTEND](#SYNTH_HDL_FRONTEND)
 - [SYNTH_HIERARCHICAL](#SYNTH_HIERARCHICAL)
 - [SYNTH_KEEP_MODULES](#SYNTH_KEEP_MODULES)
 - [SYNTH_MEMORY_MAX_BITS](#SYNTH_MEMORY_MAX_BITS)
@@ -222,6 +225,7 @@ configuration file.
 - [SYNTH_WRAPPED_OPERATORS](#SYNTH_WRAPPED_OPERATORS)
 - [TIEHI_CELL_AND_PORT](#TIEHI_CELL_AND_PORT)
 - [TIELO_CELL_AND_PORT](#TIELO_CELL_AND_PORT)
+- [VERILOG_DEFINES](#VERILOG_DEFINES)
 - [VERILOG_FILES](#VERILOG_FILES)
 - [VERILOG_INCLUDE_DIRS](#VERILOG_INCLUDE_DIRS)
 - [VERILOG_TOP_PARAMS](#VERILOG_TOP_PARAMS)

flow/designs/asap7/cva6/config.mk

@@ -1,7 +1,3 @@
-#
-# TODO before enablement: pipe VERILOG_DEFINES through to yosys
-#
-
 export PLATFORM               = asap7
 
 export DESIGN_NAME            = cva6
@@ -197,4 +193,4 @@ export PLACE_DENSITY          = 0.50
 export SKIP_LAST_GASP ?= 1
 
 
-export SYNTH_USE_SLANG = 1
+export SYNTH_HDL_FRONTEND = slang

flow/designs/asap7/ibex/config.mk

@@ -3,7 +3,13 @@ export PLATFORM               = asap7
 export DESIGN_NICKNAME        = ibex
 export DESIGN_NAME            = ibex_core
 
-export VERILOG_FILES         = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.v))
+export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/ibex_sv/*.sv)) \
+    $(DESIGN_HOME)/src/ibex_sv/syn/rtl/prim_clock_gating.v
+
+export VERILOG_INCLUDE_DIRS = \
+    $(DESIGN_HOME)/src/ibex_sv/vendor/lowrisc_ip/prim/rtl/
+
+export SYNTH_HDL_FRONTEND = slang
 
 # if FLOW_VARIANT == pos_slack, use an SDC file that has a larger clock
 # resulting in positive slack

flow/designs/gf12/ibex/config.mk

@@ -2,46 +2,13 @@ export DESIGN_NICKNAME = ibex
 export DESIGN_NAME = ibex_core
 export PLATFORM    = gf12
 
+export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/ibex_sv/*.sv)) \
+    $(DESIGN_HOME)/src/ibex_sv/syn/rtl/prim_clock_gating.v
 
-export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_alu.v \
-                       $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_branch_predict.v \
-                       $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_compressed_decoder.v \
-                       $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_controller.v \
-                       $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_core.v \
-                       $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_counter.v \
-                       $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_cs_registers.v \
-                       $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_csr.v \
-                       $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_decoder.v \
-                       $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_dummy_instr.v \
-                       $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_ex_block.v \
-                       $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_fetch_fifo.v \
-                       $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_icache.v \
-                       $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_id_stage.v \
-                       $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_if_stage.v \
-                       $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_load_store_unit.v \
-                       $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_multdiv_fast.v \
-                       $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_multdiv_slow.v \
-                       $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_pmp.v \
-                       $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_prefetch_buffer.v \
-                       $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_register_file_ff.v \
-                       $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_register_file_fpga.v \
-                       $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_register_file_latch.v \
-                       $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_wb_stage.v \
-                       $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_badbit_ram_1p.v \
-                       $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_clock_gating.v \
-                       $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_generic_clock_gating.v \
-                       $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_generic_ram_1p.v \
-                       $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_lfsr.v \
-                       $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_ram_1p.v \
-                       $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_28_22_dec.v \
-                       $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_28_22_enc.v \
-                       $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_39_32_dec.v \
-                       $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_39_32_enc.v \
-                       $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_72_64_dec.v \
-                       $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_72_64_enc.v \
-                       $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_xilinx_clock_gating.v
-
+export VERILOG_INCLUDE_DIRS = \
+    $(DESIGN_HOME)/src/ibex_sv/vendor/lowrisc_ip/prim/rtl/
 
+export SYNTH_HDL_FRONTEND = slang
 
 export SDC_FILE      = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc