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lines changed Original file line number Diff line number Diff line change @@ -23,8 +23,6 @@ export PDN_TCL = designs/asap7/mock-array-big/Element/pdn.tcl
2323# to the ring and stipe
2424export MAX_ROUTING_LAYER = M5
2525
26- export PRIVATE_DIR =designs/asap7/mock-array-big
27-
2826# If this design isn't quickly done in detailed routing, something is wrong.
2927# At time of adding this option, only 3 iterations were needed for 0
3028# violations.
Original file line number Diff line number Diff line change @@ -26,7 +26,10 @@ export IO_CONSTRAINTS = designs/asap7/mock-array-big/io.tcl
2626export PDN_TCL = designs/asap7/mock-array-big/pdn.tcl
2727export TNS_END_PERCENT = 100
2828
29- export PRIVATE_DIR =designs/asap7/mock-array-big
29+ # Target to force generation of Verilog per user settings
30+ # MOCK_ARRAY_WIDTH and MOCK_ARRAY_HEIGHT
31+ verilog :
32+ ./designs/asap7/mock-array-big/verilog.sh
3033
3134# If this design isn't quickly done in detailed routing, something is wrong.
3235# At time of adding this option, only 3 iterations were needed for 0
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