PDN_CFG --> PDN_TCL

Signed-off-by: vijayank88 <[email protected]>

Author: vijayank88

docs/user/FlowVariables.md

@@ -64,7 +64,7 @@ Note:
 | `TAPCELL_TCL`                        | =            | =            | =             | =         | =         |
 | `MACRO_PLACE_HALO`                   | ?=           | ?=           | ?=            | ?=        | ?=        |
 | `MACRO_PLACE_CHANNEL`                | ?=           | ?=           | ?=            | ?=        | ?=        |
-| `PDN_CFG`                            | ?=           | ?=           | ?=            | ?=        | ?=        |
+| `PDN_TCL`                            | ?=           | ?=           | ?=            | ?=        | ?=        |
 | `IO_PLACER_H`                        | =            | =            | =             | =         | ?=        |
 | `IO_PLACER_V`                        | =            | =            | =             | =         | ?=        |
 | Placement                            |              |              |               |           |           |
@@ -131,7 +131,7 @@ Note:
 | `MACRO_PLACE_HALO`    | horizontal/vertical halo around macros (microns). Used by automatic macro placement.                                                                               |
 | `MACRO_PLACE_CHANNEL` | horizontal/vertical channel width between macros (microns). Used by automatic macro placement when `RTLMP_FLOW` is disabled. Imagine channel=10 and halo=5. Then macros must be 10 apart but standard cells must be 5 away from a macro.|
 | `MACRO_BLOCKAGE_HALO` | Blockage width overridden from default calculation.                                                                                                                              |
-| `PDN_CFG`             | File path which has a set of power grid policies used by `pdn` to be applied to the design, such as layers to use, stripe width and spacing to generate the actual metal straps. |
+| `PDN_TCL`             | File path which has a set of power grid policies used by `pdn` to be applied to the design, such as layers to use, stripe width and spacing to generate the actual metal straps. |
 | `MAKE_TRACKS`         | Tcl file that defines add routing tracks to a floorplan.                                                                                                                         |
 | `IO_PLACER_H`         | The metal layer on which to place the I/O pins horizontally (top and bottom of the die).                                                                                         |
 | `IO_PLACER_V`         | The metal layer on which to place the I/O pins vertically (sides of the die).                                                                                                    |

flow/designs/sky130hd/chameleon_hier/config.mk

@@ -43,13 +43,10 @@ export VERILOG_FILES = \
 export HAS_IO_CONSTRAINTS = 1
 export ENABLE_DPO = 0
 export MACRO_PLACE_CHANNEL  = 160 160
-export MACRO_PLACE_HALO = 120 120
+export MACRO_PLACE_HALO = 160 160
 export DIE_AREA    = 0.0 0.0 6800 6800
 export CORE_AREA   = 200 200 6600 6600
 export SDC_FILE          = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc
 
-export FP_PDN_RAIL_WIDTH = 0.48
-export FP_PDN_RAIL_OFFSET = 0
-
 export MIN_ROUTING_LAYER = met1
 export MAX_ROUTING_LAYER = met5