scripts: whitespace consistency, tabs not spaces and misc

oharboe · oharboe · commit 557e6fea1e51 · 2025-06-26T03:42:41.000+02:00
less noisy future PRs.

Signed-off-by: Øyvind Harboe &lt;oyvind.harboe@zylin.com&gt;
diff --git a/flow/designs/gf180/uart-blocks/BLOCKS_grid_strategy.tcl b/flow/designs/gf180/uart-blocks/BLOCKS_grid_strategy.tcl
@@ -18,7 +18,7 @@ set_voltage_domain -name {CORE} -power {VDD} -ground {VSS}
 ####################################
 # standard cell grid
 ####################################
-define_pdn_grid -name {block} -voltage_domains {CORE} 
+define_pdn_grid -name {block} -voltage_domains {CORE}
 add_pdn_stripe -grid {block} -layer {Metal1} -width {0.900} -pitch {5.040} -offset {0} -followpins
 add_pdn_stripe -grid {block} -layer {Metal4} -width {4.480} -spacing {0.56} -pitch {44.8} -offset {22.4}
 add_pdn_stripe -grid {block} -layer {Metal5} -width {4.480} -pitch {89.6} -offset {44.8}
diff --git a/flow/designs/gf180/uart-blocks/uart_rx/pdn.tcl b/flow/designs/gf180/uart-blocks/uart_rx/pdn.tcl
@@ -18,7 +18,7 @@ set_voltage_domain -name {CORE} -power {VDD} -ground {VSS}
 ####################################
 # standard cell grid
 ####################################
-define_pdn_grid -name {block} -voltage_domains {CORE} 
+define_pdn_grid -name {block} -voltage_domains {CORE}
 add_pdn_stripe -grid {block} -layer {Metal1} -width {0.900} -pitch {5.040} -offset {0} -followpins
 add_pdn_stripe -grid {block} -layer {Metal4} -width {4.480} -spacing {0.56} -pitch {44.8} -offset {22.4}
 add_pdn_connect -grid {block} -layers {Metal1 Metal4}
diff --git a/flow/designs/ihp-sg13g2/i2c-gpio-expander/pdn.tcl b/flow/designs/ihp-sg13g2/i2c-gpio-expander/pdn.tcl
@@ -23,41 +23,41 @@ set_voltage_domain -name {CORE} -power {VDD} -ground {VSS}
 # stdcell grid
 define_pdn_grid -name {grid} -voltage_domains {CORE}
 add_pdn_ring \
-	-grid {grid} \
-	-layers {Metal5 TopMetal1} \
-	-widths {30.0} \
-	-spacings {5.0} \
-	-core_offsets {4.5} \
-	-connect_to_pads
+    -grid {grid} \
+    -layers {Metal5 TopMetal1} \
+    -widths {30.0} \
+    -spacings {5.0} \
+    -core_offsets {4.5} \
+    -connect_to_pads
 add_pdn_stripe \
-	-grid {grid} \
-	-layer {Metal1} \
-	-width {0.44} \
-	-pitch {7.56} \
-	-offset {0} \
-	-followpins \
-	-extend_to_core_ring
+    -grid {grid} \
+    -layer {Metal1} \
+    -width {0.44} \
+    -pitch {7.56} \
+    -offset {0} \
+    -followpins \
+    -extend_to_core_ring
 add_pdn_stripe \
-	-grid {grid} \
-	-layer {Metal5} \
-	-width {2.200} \
-	-pitch {75.6} \
-	-offset {13.600} \
-	-extend_to_core_ring
+    -grid {grid} \
+    -layer {Metal5} \
+    -width {2.200} \
+    -pitch {75.6} \
+    -offset {13.600} \
+    -extend_to_core_ring
 add_pdn_stripe \
-	-grid {grid} \
-	-layer {TopMetal1} \
-	-width {2.200} \
-	-pitch {75.6} \
-	-offset {13.600} \
-	-extend_to_core_ring
+    -grid {grid} \
+    -layer {TopMetal1} \
+    -width {2.200} \
+    -pitch {75.6} \
+    -offset {13.600} \
+    -extend_to_core_ring
 add_pdn_stripe \
-	-grid {grid} \
-	-layer {TopMetal2} \
-	-width {2.200} \
-	-pitch {75.6} \
-	-offset {13.600} \
-	-extend_to_core_ring
+    -grid {grid} \
+    -layer {TopMetal2} \
+    -width {2.200} \
+    -pitch {75.6} \
+    -offset {13.600} \
+    -extend_to_core_ring
 add_pdn_connect -grid {grid} -layers {Metal1 Metal5}
 add_pdn_connect -grid {grid} -layers {Metal5 TopMetal1}
 add_pdn_connect -grid {grid} -layers {Metal5 TopMetal2}
diff --git a/flow/platforms/asap7/openlane/config.tcl b/flow/platforms/asap7/openlane/config.tcl
@@ -15,7 +15,7 @@ set ::env(STD_CELL_GROUND_PINS) "VSS"
 set ::env(TECH_LEF) "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY)/techlef/asap7_tech_1x_201209.lef"
 set ::env(CELLS_LEF) [glob "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY)/lef/*.lef"]
 set ::env(GDS_FILES) [glob "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY)/gds/*.gds"]
-set ::env(STD_CELL_LIBRARY_CDL)	"$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY)/cdl/$::env(STD_CELL_LIBRARY).cdl"
+set ::env(STD_CELL_LIBRARY_CDL) "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY)/cdl/$::env(STD_CELL_LIBRARY).cdl"
 
 set ::env(GPIO_PADS_LEF) ""
 
@@ -25,7 +25,7 @@ set ::env(GPIO_PADS_VERILOG) ""
 set ::env(TECH_LEF_OPT) "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY_OPT)/techlef/$::env(STD_CELL_LIBRARY_OPT).tlef"
 set ::env(CELLS_LEF_OPT) [glob "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY_OPT)/lef/*.lef"]
 set ::env(GDS_FILES_OPT) [glob "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY_OPT)/gds/*.gds"]
-set ::env(STD_CELL_LIBRARY_OPT_CDL)	"$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY_OPT)/cdl/$::env(STD_CELL_LIBRARY_OPT).cdl"
+set ::env(STD_CELL_LIBRARY_OPT_CDL) "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY_OPT)/cdl/$::env(STD_CELL_LIBRARY_OPT).cdl"
 
 
 # Optimization library slowest corner
@@ -100,15 +100,15 @@ set ::env(VIAS_RC) "\
 
 # Layer RC Values
 set ::env(LAYERS_RC) "\
-	M1 1.1368e-01 1.3889e-01,\
-	M2 1.3426e-01 2.4222e-02,\
-	M3 1.2918e-01 2.4222e-02,\
-	M4 1.1396e-01 1.6778e-02,\
-	M5 1.3323e-01 1.4677e-02,\
-	M6 1.1575e-01 1.0371e-02,\
-	M7 1.3293e-01 9.6720e-03,\
-	M8 1.1822e-01 7.4310e-03,\
-	M9 1.3497e-01 6.8740e-03"
+    M1 1.1368e-01 1.3889e-01,\
+    M2 1.3426e-01 2.4222e-02,\
+    M3 1.2918e-01 2.4222e-02,\
+    M4 1.1396e-01 1.6778e-02,\
+    M5 1.3323e-01 1.4677e-02,\
+    M6 1.1575e-01 1.0371e-02,\
+    M7 1.3293e-01 9.6720e-03,\
+    M8 1.1822e-01 7.4310e-03,\
+    M9 1.3497e-01 6.8740e-03"
 
 # Extra PDN configs
 set ::env(FP_PDN_RAILS_LAYER) met1
diff --git a/flow/platforms/gf180/setRC.tcl b/flow/platforms/gf180/setRC.tcl
@@ -49,7 +49,7 @@ if { $metal == "6" } {
       }
     }
   }
-  
+
   set_wire_rc -signal -layer Metal2
   set_wire_rc -clock  -layer Metal4
 
diff --git a/flow/platforms/nangate45/tapcell.tcl b/flow/platforms/nangate45/tapcell.tcl
@@ -2,4 +2,4 @@ tapcell \
   -distance 120 \
   -tapcell_master "$::env(TAP_CELL_NAME)" \
   -endcap_master "$::env(TAP_CELL_NAME)"
-    
+
diff --git a/flow/scripts/add_routing_blk.tcl b/flow/scripts/add_routing_blk.tcl
@@ -26,15 +26,15 @@ foreach inst $allInsts {
     set w [$master getWidth]
     set h [$master getHeight]
 
-    set llx_Mx [expr $loc_llx - (128*$numTrack)] 
-    set lly_Mx [expr $loc_lly - (128*$numTrack)] 
-    set urx_Mx [expr $loc_llx + $w + (128*$numTrack)] 
-    set ury_Mx [expr $loc_lly + $h + (128*$numTrack)] 
-
-    set llx_Cx $loc_llx 
-    set lly_Cx [expr $loc_lly - (160*$numTrack)] 
-    set urx_Cx [expr $loc_llx + $w] 
-    set ury_Cx [expr $loc_lly + $h + (160*$numTrack)] 
+    set llx_Mx [expr $loc_llx - (128*$numTrack)]
+    set lly_Mx [expr $loc_lly - (128*$numTrack)]
+    set urx_Mx [expr $loc_llx + $w + (128*$numTrack)]
+    set ury_Mx [expr $loc_lly + $h + (128*$numTrack)]
+
+    set llx_Cx $loc_llx
+    set lly_Cx [expr $loc_lly - (160*$numTrack)]
+    set urx_Cx [expr $loc_llx + $w]
+    set ury_Cx [expr $loc_lly + $h + (160*$numTrack)]
 
     set obs_M2 [odb::dbObstruction_create $block $layer_M2 $llx_Mx $lly_Mx $urx_Mx $ury_Mx]
     set obs_M3 [odb::dbObstruction_create $block $layer_M3 $llx_Mx $lly_Mx $urx_Mx $ury_Mx]
diff --git a/flow/scripts/cts.tcl b/flow/scripts/cts.tcl
@@ -17,7 +17,7 @@ proc save_progress {stage} {
 set cts_args [list \
           -sink_clustering_enable \
           -balance_levels \
-	  -repair_clock_nets]
+          -repair_clock_nets]
 
 append_env_var cts_args CTS_BUF_DISTANCE -distance_between_buffers 1
 append_env_var cts_args CTS_CLUSTER_SIZE -sink_clustering_size 1
diff --git a/flow/scripts/detail_place.tcl b/flow/scripts/detail_place.tcl
@@ -10,12 +10,12 @@ proc do_dpl {} {
   if {[env_var_equals BALANCE_ROWS 1]} {
     balance_row_usage
   }
-  
+
   set_placement_padding -global \
       -left $::env(CELL_PAD_IN_SITES_DETAIL_PLACEMENT) \
       -right $::env(CELL_PAD_IN_SITES_DETAIL_PLACEMENT)
   detailed_placement
-  
+
   if {[env_var_equals ENABLE_DPO 1]} {
     if {[env_var_exists_and_non_empty DPO_MAX_DISPLACEMENT]} {
       improve_placement -max_displacement $::env(DPO_MAX_DISPLACEMENT)
@@ -26,7 +26,7 @@ proc do_dpl {} {
   optimize_mirroring
 
   utl::info FLW 12 "Placement violations [check_placement -verbose]."
-  
+
   estimate_parasitics -placement
 }
 
diff --git a/flow/scripts/load.tcl b/flow/scripts/load.tcl
@@ -8,7 +8,7 @@ proc load_design {design_file sdc_file} {
   if {[env_var_exists_and_non_empty PLATFORM_TCL]} {
     log_cmd source $::env(PLATFORM_TCL)
   }
-  
+
   # Read liberty files
   source $::env(SCRIPTS_DIR)/read_liberty.tcl
 
@@ -46,7 +46,7 @@ proc load_design {design_file sdc_file} {
 }
 
 #===========================================================================================
-# Routines to run equivalence tests when they are enabled. 
+# Routines to run equivalence tests when they are enabled.
 
 proc get_verilog_cells_for_design { } {
     set dir "$::env(PLATFORM_DIR)/work_around_yosys/"
@@ -98,7 +98,7 @@ proc write_eqy_script { } {
     # Gold netlist
     puts $outfile "\[gold]\nread_verilog -sv $::env(RESULTS_DIR)/4_before_rsz.v $cell_files\n"
     puts $outfile "prep -top $top_cell -flatten\nmemory_map\n\n"
-    # Modified netlist 
+    # Modified netlist
     puts $outfile "\[gate]\nread_verilog -sv $::env(RESULTS_DIR)/4_after_rsz.v $cell_files\n"
     puts $outfile "prep -top $top_cell -flatten\nmemory_map\n\n"
 
diff --git a/flow/scripts/macro_place_util.tcl b/flow/scripts/macro_place_util.tcl
@@ -74,7 +74,7 @@ if {[find_macros] != ""} {
   }
 
   source $::env(SCRIPTS_DIR)/placement_blockages.tcl
-  block_channels $blockage_width 
+  block_channels $blockage_width
 } else {
   puts "No macros found: Skipping macro_placement"
 }
diff --git a/flow/scripts/open.tcl b/flow/scripts/open.tcl
@@ -31,13 +31,13 @@ proc read_timing {input_file} {
   if [file exists $::env(PLATFORM_DIR)/derate.tcl] {
     source $::env(PLATFORM_DIR)/derate.tcl
   }
-  
+
   source $::env(PLATFORM_DIR)/setRC.tcl
   if {$design_stage >= 4} {
     # CTS has run, so propagate clocks
     set_propagated_clock [all_clocks]
   }
-  
+
   if {$design_stage >= 6 && [file exist $::env(RESULTS_DIR)/6_final.spef]} {
     log_cmd read_spef $::env(RESULTS_DIR)/6_final.spef
   } elseif {$design_stage >= 5} {
diff --git a/flow/scripts/report_metrics.tcl b/flow/scripts/report_metrics.tcl
@@ -154,17 +154,17 @@ proc report_metrics { stage when {include_erc true} {include_clock_skew true} }
     report_puts "\n=========================================================================="
     report_puts "$when report_checks -path_delay max reg to reg"
     report_puts "--------------------------------------------------------------------------"
-    report_checks -path_delay max -from [all_registers] -to [all_registers] -format full_clock_expanded >> $filename    
+    report_checks -path_delay max -from [all_registers] -to [all_registers] -format full_clock_expanded >> $filename
     report_puts "\n=========================================================================="
     report_puts "$when report_checks -path_delay min reg to reg"
     report_puts "--------------------------------------------------------------------------"
-    report_checks -path_delay min -from [all_registers] -to [all_registers]  -format full_clock_expanded >> $filename         
+    report_checks -path_delay min -from [all_registers] -to [all_registers]  -format full_clock_expanded >> $filename
 
     set inp_to_reg_critical_path [lindex [find_timing_paths -path_delay max -from [all_inputs] -to [all_registers]] 0]
     if {$inp_to_reg_critical_path != ""} {
       set target_clock_latency_max [sta::format_time [$inp_to_reg_critical_path target_clk_delay] 4]
     } else {
-      set target_clock_latency_max 0	
+      set target_clock_latency_max 0
     }
 
 
@@ -173,10 +173,10 @@ proc report_metrics { stage when {include_erc true} {include_clock_skew true} }
       set target_clock_latency_min [sta::format_time [$inp_to_reg_critical_path target_clk_delay] 4]
       set source_clock_latency [sta::format_time [$inp_to_reg_critical_path source_clk_latency] 4]
     } else {
-      set target_clock_latency_min 0	
+      set target_clock_latency_min 0
       set source_clock_latency 0
     }
-      
+
     report_puts "\n=========================================================================="
     report_puts "$when critical path target clock latency max path"
     report_puts "--------------------------------------------------------------------------"
@@ -195,7 +195,7 @@ proc report_metrics { stage when {include_erc true} {include_clock_skew true} }
     puts "No registers in design"
     }
     # end if all_registers
-      
+
     report_puts "\n=========================================================================="
     report_puts "$when critical path delay"
     report_puts "--------------------------------------------------------------------------"
diff --git a/flow/scripts/synth_preamble.tcl b/flow/scripts/synth_preamble.tcl
@@ -27,7 +27,7 @@ proc read_checkpoint {file} {
     read_json $file
   } else {
     read_rtlil $file
-  }  
+  }
 }
 
 proc read_design_sources {} {
@@ -53,10 +53,10 @@ proc read_design_sources {} {
     setattr -unset init
   } elseif {[env_var_equals SYNTH_HDL_FRONTEND verific]} {
     if {[env_var_exists_and_non_empty VERILOG_INCLUDE_DIRS]} {
-	    verific -vlog-incdir {*}$::env(VERILOG_INCLUDE_DIRS)
+        verific -vlog-incdir {*}$::env(VERILOG_INCLUDE_DIRS)
     }
     if {[env_var_exists_and_non_empty VERILOG_DEFINES]} {
-	    verific -vlog-define {*}$::env(VERILOG_DEFINES)
+        verific -vlog-define {*}$::env(VERILOG_DEFINES)
     }
     verific -sv2012 {*}$::env(VERILOG_FILES)
   } elseif {![env_var_exists_and_non_empty SYNTH_HDL_FRONTEND]} {
@@ -69,7 +69,7 @@ proc read_design_sources {} {
     }
     verilog_defaults -pop
   } else {
-    error "Unrecognized HDL frontend: $::env(SYNTH_HDL_FRONTEND)" 
+    error "Unrecognized HDL frontend: $::env(SYNTH_HDL_FRONTEND)"
   }
 
   # Read platform specific mapfile for OPENROAD_CLKGATE cells
diff --git a/flow/scripts/synth_wrap_operators.tcl b/flow/scripts/synth_wrap_operators.tcl
@@ -53,7 +53,7 @@ foreach info $deferred_cells {
   # iterate over all architectures, both the default and non-default
   foreach arch [lrange $info 2 end] {
     set suffix [lindex $arch 0]
-    set extra_map_args [lrange $arch 1 end] 
+    set extra_map_args [lrange $arch 1 end]
 
     # map all operator copies which were selected to have this architecture
     techmap -map +/techmap.v {*}$extra_map_args A:source_cell=$type A:architecture=$suffix %i
diff --git a/flow/scripts/util.tcl b/flow/scripts/util.tcl
@@ -151,9 +151,9 @@ proc find_macros {} {
 proc erase_non_stage_variables {stage_name} {
   # "$::env(SCRIPTS_DIR)/stage_variables.py stage_name" returns list of
   # variables to erase.
-  # 
+  #
   # Tcl yaml package can't be imported in the sta/openroad environment:
-  # 
+  #
   # https://github.com/The-OpenROAD-Project/OpenROAD/issues/5875
   set variables [exec $::env(SCRIPTS_DIR)/non_stage_variables.py $stage_name]
   foreach var $variables {
diff --git a/flow/scripts/write_ref_sdc.tcl b/flow/scripts/write_ref_sdc.tcl
@@ -19,7 +19,7 @@ if { [llength $clks] == 0 } {
       set ref_period [expr ($period - $slack) * (1.0 - $margin/100.0)]
       utl::info "FLW" 8 "Clock $clk_name period [format %.3f $ref_period]"
       utl::info "FLW" 9 "Clock $clk_name slack [format %.3f $slack]"
-  
+
       set sources [$clk sources]
       # Redefine clock with updated period.
       create_clock -name $clk_name -period $ref_period $sources
diff --git a/flow/tutorials/scripts/drt/helpers.tcl b/flow/tutorials/scripts/drt/helpers.tcl
@@ -14,7 +14,7 @@ proc make_result_file { filename } {
 # puts [exec cat $file] without forking.
 proc report_file { file } {
   set stream [open $file r]
-  
+
   while { [gets $stream line] >= 0 } {
     puts $line
   }
@@ -24,7 +24,7 @@ proc report_file { file } {
 proc diff_files { file1 file2 } {
   set stream1 [open $file1 r]
   set stream2 [open $file2 r]
-  
+
   set line 1
   set diff_line 0;
   while { [gets $stream1 line1] >= 0 && [gets $stream2 line2] >= 0 } {
diff --git a/flow/util/cell-veneer/lefdef.tcl b/flow/util/cell-veneer/lefdef.tcl
diff --git a/flow/util/cell-veneer/wrap_stdcells.tcl b/flow/util/cell-veneer/wrap_stdcells.tcl
diff --git a/flow/util/write_net_rc.tcl b/flow/util/write_net_rc.tcl

Original file line number	Diff line number	Diff line change
`@@ -49,7 +49,7 @@ if { $metal == "6" } {`
`49`	`49`	`}`
`50`	`50`	`}`
`51`	`51`	`}`
`52`		`-`
	`52`	`+`
`53`	`53`	`set_wire_rc -signal -layer Metal2`
`54`	`54`	`set_wire_rc -clock -layer Metal4`
`55`	`55`