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lines changed Original file line number Diff line number Diff line change @@ -338,13 +338,28 @@ CTS_ARGS:
338338HOLD_SLACK_MARGIN :
339339 description : >
340340 Specifies a time margin for the slack when fixing hold violations.
341- This option allows you to overfix.
341+ This option allows you to overfix or underfix(negative value, terminate
342+ retiming before 0 or positive slack).
343+ stages :
344+ - cts
345+ - floorplan
346+ - grt
342347SETUP_SLACK_MARGIN :
343348 description : >
344349 Specifies a time margin for the slack when fixing setup violations.
350+ This option allows you to overfix or underfix(negative value, terminate
351+ retiming before 0 or positive slack).
352+ stages :
353+ - cts
354+ - floorplan
355+ - grt
345356SKIP_GATE_CLONING :
346357 description : >
347358 Do not use gate cloning transform to fix timing violations (default: use gate cloning).
359+ stages :
360+ - cts
361+ - floorplan
362+ - grt
348363SKIP_LAST_GASP :
349364 description : >
350365 Do not use last gasp optimization to fix timing violations (default: use gate last gasp).
@@ -355,6 +370,10 @@ SKIP_LAST_GASP:
355370SKIP_PIN_SWAP :
356371 description : >
357372 Do not use pin swapping as a transform to fix timing violations (default: use pin swapping).
373+ stages :
374+ - cts
375+ - floorplan
376+ - grt
358377REMOVE_CELLS_FOR_EQY :
359378 description : >
360379 String patterns directly passed to write_verilog -remove_cells <> for equivalence checks.
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