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Commit 62a84f5

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author
Ravi Varadarajan
committed
bp_quad (block) updates for NG45 and gf12
Signed-off-by: Ravi Varadarajan <[email protected]>
1 parent 2b4010b commit 62a84f5

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4 files changed

+21
-160
lines changed

4 files changed

+21
-160
lines changed
Lines changed: 14 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -1,15 +1,16 @@
11
export DESIGN_NICKNAME = bp_quad
22
export DESIGN_NAME = bsg_chip
33
export PLATFORM = gf12
4-
export FLOW_VARIANT = synth
4+
5+
export RTLMP_FLOW = True
56
export SYNTH_HIERARCHICAL = 1
6-
export MAX_UNGROUP_SIZE ?= 10000
7+
export MAX_UNGROUP_SIZE ?= 1000
8+
9+
export CACHED_NETLIST = $(PLATFORM_DIR)/bp/bsg_ac_black_parrot_quad_core_v0/bp_quad_block/yosys/bp_quad_yosys_netlist.v
10+
export VERILOG_FILES = $(PLATFORM_DIR)/bp/bsg_ac_black_parrot_quad_core_v0/bp_quad_block/rtl/bsg_chip_block.sv2v.v
711

8-
export CACHED_NETLIST = $(PLATFORM_DIR)/bp/bsg_ac_black_parrot_dual_core_v0/yosys/bp_dual_hier_yosys_netlist.v
9-
export VERILOG_FILES = $(PLATFORM_DIR)/bp/bsg_ac_black_parrot_quad_core_v0/bsg_chip.sv2v.v \
10-
$(PLATFORM_DIR)/bp/IN12LP_GPIO18_13M9S30P.blackbox.v
1112

12-
export SDC_FILE = $(PLATFORM_DIR)/bp/bsg_ac_black_parrot_quad_core_v0/bsg_chip.elab.v.sdc
13+
export SDC_FILE = $(PLATFORM_DIR)/bp/bsg_ac_black_parrot_quad_core_v0/bp_quad_block/sdc/bsg_chip.sdc
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1415
export WRAP_LEFS = $(PLATFORM_DIR)/lef/gf12_1r1w_d32_w64_m1.lef \
1516
$(PLATFORM_DIR)/lef/gf12_1rw_d128_w116_m2_bit.lef \
@@ -18,17 +19,13 @@ export WRAP_LEFS = $(PLATFORM_DIR)/lef/gf12_1r1w_d32_w64_m1.lef \
1819
$(PLATFORM_DIR)/lef/gf12_1rw_d64_w124_m2_bit.lef \
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$(PLATFORM_DIR)/lef/gf12_1rw_d64_w62_m2_bit.lef
2021

21-
export ADDITIONAL_LEFS = $(PLATFORM_DIR)/lef/IN12LP_GPIO18_13M9S30P.lef \
22-
$(PLATFORM_DIR)/lef/CDMM_13M_3Mx_2Cx_4Kx_2Hx_2Gx_LB.lef
23-
2422
export WRAP_LIBS = $(PLATFORM_DIR)/lib/gf12_1r1w_d32_w64_m1_ffpg_sigcmin_0p88v_0p88v_m40c.lib \
2523
$(PLATFORM_DIR)/lib/gf12_1rw_d128_w116_m2_bit_ffpg_sigcmin_0p88v_0p88v_m40c.lib \
2624
$(PLATFORM_DIR)/lib/gf12_1rw_d256_w48_m2_ffpg_sigcmin_0p88v_0p88v_m40c.lib \
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$(PLATFORM_DIR)/lib/gf12_1rw_d512_w64_m2_byte_ffpg_sigcmin_0p88v_0p88v_m40c.lib \
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$(PLATFORM_DIR)/lib/gf12_1rw_d64_w124_m2_bit_ffpg_sigcmin_0p88v_0p88v_m40c.lib \
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$(PLATFORM_DIR)/lib/gf12_1rw_d64_w62_m2_bit_ffpg_sigcmin_0p88v_0p88v_m40c.lib
3028

31-
export ADDITIONAL_LIBS = $(PLATFORM_DIR)/lib/IN12LP_GPIO18_13M9S30P_TT_0P8_1P8_25.lib
3229

3330
export ADDITIONAL_GDS = $(PLATFORM_DIR)/gds/gf12_1r1w_d32_w64_m1.gds2 \
3431
$(PLATFORM_DIR)/gds/gf12_1rw_d128_w116_m2_bit.gds2 \
@@ -41,18 +38,18 @@ export ADDITIONAL_GDS = $(PLATFORM_DIR)/gds/gf12_1r1w_d32_w64_m1.gds2 \
4138

4239
export SEAL_GDS = $(PLATFORM_DIR)/gds/crackstop_3x3.gds
4340

41+
export DIE_AREA = 0 0 1800 1800
42+
export CORE_AREA = 5 5 1795 1795
43+
export PLACE_PINS_ARGS = -exclude left:* -exclude right:* -exclude top:* -exclude bottom:0-800 -exclude bottom:1200-1800
44+
export HAS_IO_CONSTRAINTS = 1
4445

45-
export FOOTPRINT = $(PLATFORM_DIR)/bp/bsg_bp_quad.package.strategy
46-
export SIG_MAP_FILE = $(PLATFORM_DIR)/bp/soc_bsg_black_parrot.sigmap
47-
48-
export ABC_CLOCK_PERIOD_IN_PS = 1250
4946

50-
export PLACE_DENSITY = 0.40
47+
export PLACE_DENSITY_LB_ADDON = 0.02
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5249
export MACRO_WRAPPERS = $(PLATFORM_DIR)/bp/wrappers/wrappers.tcl
5350

5451
export PDN_TCL = $(PLATFORM_DIR)/cfg/pdn_grid_strategy_13m_9T.top.tcl
5552

5653
# Define macro halo and channel spacings
57-
export MACRO_PLACE_HALO = 0 0
58-
export MACRO_PLACE_CHANNEL = 30.24 30.24
54+
export MACRO_PLACE_HALO = 5 5
55+
export MACRO_PLACE_CHANNEL = 10 10

flow/designs/gf12/bp_quad/config_hier.mk

Lines changed: 0 additions & 69 deletions
This file was deleted.

flow/designs/gf12/bp_quad/config_synth.mk

Lines changed: 0 additions & 67 deletions
This file was deleted.

flow/designs/nangate45/bp_quad/config.mk

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -6,10 +6,10 @@ export SYNTH_HIERARCHICAL = 1
66
export RTLMP_FLOW = True
77

88
# RTL_MP Settings
9-
export RTLMP_MAX_INST = 30000
10-
export RTLMP_MIN_INST = 5000
11-
export RTLMP_MAX_MACRO = 16
12-
export RTLMP_MIN_MACRO = 4
9+
#export RTLMP_MAX_INST = 30000
10+
#export RTLMP_MIN_INST = 5000
11+
#export RTLMP_MAX_MACRO = 16
12+
#export RTLMP_MIN_MACRO = 4
1313

1414
export VERILOG_FILES = ./designs/src/$(DESIGN_NICKNAME)/bsg_chip_block.sv2v.v \
1515
./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/macros.v
@@ -30,10 +30,10 @@ export ADDITIONAL_LIBS = $(PLATFORM_DIR)/lib/fakeram45_256x48.lib \
3030
$(PLATFORM_DIR)/lib/fakeram45_64x62.lib \
3131
$(PLATFORM_DIR)/lib/fakeram45_128x116.lib
3232

33-
export DIE_AREA = 0 0 1500 1500
34-
export CORE_AREA = 10 12 1448 1448
33+
export DIE_AREA = 0 0 3600 3600
34+
export CORE_AREA = 10 12 3590 3590
3535

36-
export PLACE_PINS_ARGS = -exclude left:0-500 -exclude left:1000-1500: -exclude right:* -exclude top:* -exclude bottom:*
36+
export PLACE_PINS_ARGS = -exclude left:* -exclude right:* -exclude top:* -exclude bottom:0-1000 -exclude bottom:2400-3600
3737

3838
export MACRO_PLACE_HALO = 10 10
3939
export MACRO_PLACE_CHANNEL = 20 20

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