mock-array: clean out FLOW_HOME usage, use more specific variables such as RESULTS_DIR

Signed-off-by: Øyvind Harboe <[email protected]>

Author: oharboe

flow/designs/asap7/mock-array/Element/config.mk

@@ -24,7 +24,7 @@ export DIE_AREA = $(shell \
 
 export IO_CONSTRAINTS         = designs/asap7/mock-array/Element/io.tcl
 
-export PDN_TCL                = $(FLOW_HOME)/platforms/asap7/openRoad/pdn/BLOCK_grid_strategy.tcl
+export PDN_TCL                = $(PLATFORM_DIR)/openRoad/pdn/BLOCK_grid_strategy.tcl
 
 # Detailed routing should be easy, limit iterations
 export DETAILED_ROUTE_END_ITERATION ?= 6

flow/designs/asap7/mock-array/simulate.sh

@@ -13,8 +13,8 @@ mkdir -p $OBJ_DIR
 mkdir -p $POST_DIR
 
 # Copy Verilog files used for simulation to post dir in the objects area
-cp $FLOW_HOME/results/asap7/mock-array/base/6_final.v $POST_DIR/MockArrayFinal.v
-cp $FLOW_HOME/results/asap7/mock-array_Element/base/6_final.v $POST_DIR/MockArrayElement.v
+cp $RESULTS_DIR/6_final.v $POST_DIR/MockArrayFinal.v
+cp $RESULTS_DIR/../../mock-array_Element/base/6_final.v $POST_DIR/MockArrayElement.v
 
 # Run simulation and have Verilator write the output files to the objects area
 verilator -Wall --cc \
@@ -31,10 +31,10 @@ verilator -Wall --cc \
   $PLATFORM_DIR/verilog/stdcell/asap7sc7p5t_SIMPLE_RVT_TT_201020.v \
   $PLATFORM_DIR/verilog/stdcell/dff.v \
   $PLATFORM_DIR/verilog/stdcell/empty.v \
-  $FLOW_HOME/results/asap7/mock-array/base/6_final.v \
-  $FLOW_HOME/results/asap7/mock-array_Element/base/6_final.v \
+  $RESULTS_DIR/6_final.v \
+  $RESULTS_DIR/../../mock-array_Element/base/6_final.v \
   --exe \
-  $FLOW_HOME/designs/src/mock-array/simulate.cpp
+  $DESIGN_HOME/src/mock-array/simulate.cpp
 
 # Link the generated object files into the VMockArray executable
 make -j16 -C $OBJ_DIR -f VMockArray.mk