File tree Expand file tree Collapse file tree 3 files changed +34
-1
lines changed
designs/gf180/uart-blocks/uart_rx Expand file tree Collapse file tree 3 files changed +34
-1
lines changed Original file line number Diff line number Diff line change @@ -11,7 +11,7 @@ export CORE_ASPECT_RATIO = 1
1111export CORE_MARGIN = 2
1212export PLACE_DENSITY = 0.60
1313
14- export PDN_TCL = $(DESIGN_HOME ) /$(PLATFORM ) /uart-blocks/BLOCKS_grid_strategy .tcl
14+ export PDN_TCL = $(DESIGN_HOME ) /$(PLATFORM ) /uart-blocks/uart_rx/pdn .tcl
1515
1616export PLACE_PINS_ARGS = -exclude bottom :* -exclude top:* -exclude right:*
1717
Original file line number Diff line number Diff line change 1+ # ###################################
2+ # global connections
3+ # ###################################
4+ add_global_connection -net {VDD} -inst_pattern {.*} -pin_pattern {^VDD$} -power
5+ add_global_connection -net {VDD} -inst_pattern {.*} -pin_pattern {^VDDPE$}
6+ add_global_connection -net {VDD} -inst_pattern {.*} -pin_pattern {^VDDCE$}
7+ add_global_connection -net {VDD} -inst_pattern {.*} -pin_pattern {^VDDP$}
8+ add_global_connection -net {VDD} -inst_pattern {.*} -pin_pattern {^VDDC$}
9+ add_global_connection -net {VDD} -inst_pattern {.*} -pin_pattern {^VNW$}
10+ add_global_connection -net {VSS} -inst_pattern {.*} -pin_pattern {^VSS$} -ground
11+ add_global_connection -net {VSS} -inst_pattern {.*} -pin_pattern {^VSSE$}
12+ add_global_connection -net {VSS} -inst_pattern {.*} -pin_pattern {^VSSC$}
13+ add_global_connection -net {VSS} -inst_pattern {.*} -pin_pattern {^VPW$}
14+ # ###################################
15+ # voltage domains
16+ # ###################################
17+ set_voltage_domain -name {CORE} -power {VDD} -ground {VSS}
18+ # ###################################
19+ # standard cell grid
20+ # ###################################
21+ define_pdn_grid -name {block} -voltage_domains {CORE}
22+ add_pdn_stripe -grid {block} -layer {Metal1} -width {0.900} -pitch {5.040} -offset {0} -followpins
23+ add_pdn_stripe -grid {block} -layer {Metal4} -width {4.480} -spacing {0.56} -pitch {44.8} -offset {22.4}
24+ add_pdn_connect -grid {block} -layers {Metal1 Metal4}
Original file line number Diff line number Diff line change @@ -120,20 +120,29 @@ export RCX_RC_CORNER = $($(CORNER)_RCX_RC_CORNER)
120120# ----------------------------------------------------------------------------------------------------
121121export BC_LIB_FILES = $(abspath $(PLATFORM_DIR ) /lib/gf180mcu_fd_sc_mcu$(TRACK_OPTION )$(POWER_OPTION ) __ff_n40C_5v50.lib.gz)
122122export BC_TEMPERATURE = -40c
123+ export BC_VOLTAGE = 5.5
123124
124125export WC_LIB_FILES = $(abspath $(PLATFORM_DIR ) /lib/gf180mcu_fd_sc_mcu$(TRACK_OPTION )$(POWER_OPTION ) __ss_125C_4v50.lib.gz)
125126export WC_TEMPERATURE = 125c
127+ export WC_VOLTAGE = 4.5
126128
127129export TC_LIB_FILES = $(abspath $(PLATFORM_DIR ) /lib/gf180mcu_fd_sc_mcu$(TRACK_OPTION )$(POWER_OPTION ) __tt_025C_5v00.lib.gz)
128130export TC_TEMPERATURE = 25c
131+ export TC_VOLTAGE = 5.0
129132
130133# ----------------------------------------------------------------------------------------------------
131134# now, set files from user setting CORNER
132135# ----------------------------------------------------------------------------------------------------
133136export TEMPERATURE = $($(CORNER ) _TEMPERATURE)
137+ export VOLTAGE = $($(CORNER ) _VOLTAGE)
134138export LIB_FILES = $($(CORNER ) _LIB_FILES) \
135139 $(ADDITIONAL_LIBS )
136140
141+ # IR drop estimation supply net name to be analyzed and supply voltage variable
142+ export PWR_NETS_VOLTAGES ?= VDD $(VOLTAGE )
143+ export GND_NETS_VOLTAGES ?= VSS 0.0
144+ export IR_DROP_LAYER ?= Metal1
145+
137146# For proprietary tool enablements that are not public
138147export GF180_PRIVATE_DIR ?= ../../gf180-private
139148-include $(GF180_PRIVATE_DIR ) /private.mk
You can’t perform that action at this time.
0 commit comments