fix PR merge mistake

Signed-off-by: Tom Spyrou <[email protected]>

Author: tspyrou

flow/designs/asap7/mock-array/constraints.sdc

@@ -13,6 +13,7 @@ set_clock_uncertainty 10 [get_clocks $clk_name]
 
 create_clock -name ${clk_name}_vir -period $clk_period -waveform [list 0 [expr $clk_period/2]]
 set_clock_uncertainty  10 [get_clocks ${clk_name}_vir]
+set_clock_latency 380 [get_clocks ${clk_name}_vir] ;# Matching real clock latency
 
 set clk_port [get_ports $clk_port_name]
 set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]