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malibertymaliberty
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Merge pull request #1062 from vijayank88/chameleon_fix
chameleon_hier updates for BLOCKS
2 parents 5d9b74e + 4fe0f30 commit 76b6e12

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‎docs/user/FlowVariables.md‎

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@@ -64,7 +64,7 @@ Note:
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| `TAPCELL_TCL` | = | = | = | = | = |
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| `MACRO_PLACE_HALO` | ?= | ?= | ?= | ?= | ?= |
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| `MACRO_PLACE_CHANNEL` | ?= | ?= | ?= | ?= | ?= |
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| `PDN_CFG` | ?= | ?= | ?= | ?= | ?= |
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| `PDN_TCL` | ?= | ?= | ?= | ?= | ?= |
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| `IO_PLACER_H` | = | = | = | = | ?= |
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| `IO_PLACER_V` | = | = | = | = | ?= |
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| Placement | | | | | |
@@ -131,7 +131,7 @@ Note:
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| `MACRO_PLACE_HALO` | horizontal/vertical halo around macros (microns). Used by automatic macro placement. |
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| `MACRO_PLACE_CHANNEL` | horizontal/vertical channel width between macros (microns). Used by automatic macro placement when `RTLMP_FLOW` is disabled. Imagine channel=10 and halo=5. Then macros must be 10 apart but standard cells must be 5 away from a macro.|
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| `MACRO_BLOCKAGE_HALO` | Blockage width overridden from default calculation. |
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| `PDN_CFG` | File path which has a set of power grid policies used by `pdn` to be applied to the design, such as layers to use, stripe width and spacing to generate the actual metal straps. |
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| `PDN_TCL` | File path which has a set of power grid policies used by `pdn` to be applied to the design, such as layers to use, stripe width and spacing to generate the actual metal straps. |
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| `MAKE_TRACKS` | Tcl file that defines add routing tracks to a floorplan. |
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| `IO_PLACER_H` | The metal layer on which to place the I/O pins horizontally (top and bottom of the die). |
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| `IO_PLACER_V` | The metal layer on which to place the I/O pins vertically (sides of the die). |

‎flow/Makefile‎

Lines changed: 1 addition & 1 deletion
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@@ -471,7 +471,7 @@ $(RESULTS_DIR)/2_5_floorplan_tapcell.odb: $(RESULTS_DIR)/2_4_floorplan_macro.odb
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# STEP 6: PDN generation
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#-------------------------------------------------------------------------------
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$(RESULTS_DIR)/2_6_floorplan_pdn.odb: $(RESULTS_DIR)/2_5_floorplan_tapcell.odb $(PDN_CFG) $(PDN_TCL)
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$(RESULTS_DIR)/2_6_floorplan_pdn.odb: $(RESULTS_DIR)/2_5_floorplan_tapcell.odb $(PDN_TCL)
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($(TIME_CMD) $(OPENROAD_CMD) $(SCRIPTS_DIR)/pdn.tcl -metrics $(LOG_DIR)/2_6_pdn.json) 2>&1 | tee $(LOG_DIR)/2_6_pdn.log
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$(RESULTS_DIR)/2_floorplan.odb: $(RESULTS_DIR)/2_6_floorplan_pdn.odb

‎flow/designs/sky130hd/chameleon_hier/BLOCKS_pdn.tcl‎

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@@ -0,0 +1,24 @@
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####################################
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# global connections
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####################################
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add_global_connection -net {VDD} -inst_pattern {.*} -pin_pattern {^VDD$} -power
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add_global_connection -net {VDD} -inst_pattern {.*} -pin_pattern {^VDDPE$}
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add_global_connection -net {VDD} -inst_pattern {.*} -pin_pattern {^VDDCE$}
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add_global_connection -net {VDD} -inst_pattern {.*} -pin_pattern {VPWR}
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add_global_connection -net {VDD} -inst_pattern {.*} -pin_pattern {VPB}
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add_global_connection -net {VSS} -inst_pattern {.*} -pin_pattern {^VSS$} -ground
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add_global_connection -net {VSS} -inst_pattern {.*} -pin_pattern {^VSSE$}
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add_global_connection -net {VSS} -inst_pattern {.*} -pin_pattern {VGND}
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add_global_connection -net {VSS} -inst_pattern {.*} -pin_pattern {VNB}
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global_connect
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####################################
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# voltage domains
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####################################
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set_voltage_domain -name {CORE} -power {VDD} -ground {VSS}
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####################################
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# standard cell grid
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####################################
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define_pdn_grid -name {grid} -voltage_domains {CORE}
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add_pdn_stripe -grid {grid} -layer {met1} -width {0.48} -pitch {5.44} -offset {0} -followpins
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add_pdn_stripe -grid {grid} -layer {met4} -width {1.600} -pitch {27.140} -offset {13.570}
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add_pdn_connect -grid {grid} -layers {met1 met4}

‎flow/designs/sky130hd/chameleon_hier/DFFRAM_4K/config.mk‎

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@@ -13,13 +13,13 @@ export VERILOG_FILES = \
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export SDC_FILE = ${TOP_DIR}/${DESIGN_NAME}/constraint.sdc
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export PDN_CFG = ${TOP_DIR}/${DESIGN_NAME}/pdn.cfg
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export PDN_TCL = ${TOP_DIR}/BLOCKS_pdn.tcl
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export ABC_DRIVER_CELL = sky130_fd_sc_hd__buf_1
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export ABC_LOAD_IN_FF = 3
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# These values must be multiples of placement site
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export DIE_AREA = 0 0 1925 2450
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export CORE_AREA = 0.46 2.720 1924.54 2447.28
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export MIN_ROUTING_LAYER 2
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export MAX_ROUTING_LAYER 5
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export MIN_ROUTING_LAYER = met1
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export MAX_ROUTING_LAYER = met4

‎flow/designs/sky130hd/chameleon_hier/DFFRAM_4K/pdn.cfg‎

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This file was deleted.

‎flow/designs/sky130hd/chameleon_hier/DMC_32x16HC/config.mk‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -13,7 +13,7 @@ export VERILOG_FILES = \
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export SDC_FILE = ${TOP_DIR}/${DESIGN_NAME}/constraint.sdc
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export PDN_CFG = ${TOP_DIR}/${DESIGN_NAME}/pdn.cfg
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export PDN_TCL = ${TOP_DIR}/BLOCKS_pdn.tcl
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export ABC_DRIVER_CELL = sky130_fd_sc_hd__buf_1
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export ABC_LOAD_IN_FF = 3
@@ -22,5 +22,5 @@ export ABC_LOAD_IN_FF = 3
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export DIE_AREA = 0 0 600 900
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export CORE_AREA = 0.46 2.720 599.54 897.28
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export MIN_ROUTING_LAYER 2
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export MAX_ROUTING_LAYER 5
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export MIN_ROUTING_LAYER = met1
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export MAX_ROUTING_LAYER = met4

‎flow/designs/sky130hd/chameleon_hier/DMC_32x16HC/pdn.cfg‎

Lines changed: 0 additions & 37 deletions
This file was deleted.

‎flow/designs/sky130hd/chameleon_hier/apb_sys_0/config.mk‎

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@@ -13,7 +13,7 @@ export VERILOG_FILES = \
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export SDC_FILE = ${TOP_DIR}/${DESIGN_NAME}/constraint.sdc
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export PDN_CFG = ${TOP_DIR}/${DESIGN_NAME}/pdn.cfg
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export PDN_TCL = ${TOP_DIR}/BLOCKS_pdn.tcl
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export ABC_DRIVER_CELL = sky130_fd_sc_hd__buf_1
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export ABC_LOAD_IN_FF = 3
@@ -22,5 +22,5 @@ export ABC_LOAD_IN_FF = 3
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export DIE_AREA = 0 0 675 1050
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export CORE_AREA = 0.46 2.720 674.54 1047.28
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export MIN_ROUTING_LAYER 2
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export MAX_ROUTING_LAYER 5
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export MIN_ROUTING_LAYER = met1
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export MAX_ROUTING_LAYER = met4

‎flow/designs/sky130hd/chameleon_hier/apb_sys_0/pdn.cfg‎

Lines changed: 0 additions & 37 deletions
This file was deleted.

‎flow/designs/sky130hd/chameleon_hier/config.mk‎

Lines changed: 3 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -43,16 +43,10 @@ export VERILOG_FILES = \
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export HAS_IO_CONSTRAINTS = 1
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export ENABLE_DPO = 0
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export MACRO_PLACE_CHANNEL = 160 160
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export MACRO_PLACE_HALO = 2 2
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export MACRO_PLACE_HALO = 160 160
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export DIE_AREA = 0.0 0.0 6800 6800
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export CORE_AREA = 200 200 6600 6600
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export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc
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export RCX_RULES = $(PLATFORM_DIR)/rcx_patterns.rules
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export PDN_CFG = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/pdn.cfg
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export FP_PDN_RAIL_WIDTH = 0.48
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export FP_PDN_RAIL_OFFSET = 0
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export MIN_ROUTING_LAYER 2
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export MAX_ROUTING_LAYER 6
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export MIN_ROUTING_LAYER = met1
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export MAX_ROUTING_LAYER = met5

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