Merge pull request #2149 from Pinata-Consulting/mock-array-post-synthesis-simulation

mock-array: read_power_activities MockArray.vcd test case

Author: maliberty

flow/designs/asap7/mock-array/config.mk

@@ -40,6 +40,16 @@ verilog:
 	export MOCK_ARRAY_COLS=$(word 2, $(MOCK_ARRAY_TABLE)) ; \
 	./designs/asap7/mock-array/verilog.sh
 
+.PHONY: simulate
+simulate:
+	export MOCK_ARRAY_ROWS=$(word 1, $(MOCK_ARRAY_TABLE)) ; \
+	export MOCK_ARRAY_COLS=$(word 2, $(MOCK_ARRAY_TABLE)) ; \
+	./designs/asap7/mock-array/simulate.sh
+
+.PHONY: power
+power:
+	$(OPENSTA_EXE) -no_init -exit designs/asap7/mock-array/power.tcl
+
 # If this design isn't quickly done in detailed routing, something is wrong.
 # At time of adding this option, only 12 iterations were needed for 0
 # violations.

flow/designs/asap7/mock-array/power.tcl

@@ -0,0 +1,24 @@
+foreach libFile $::env(LIB_FILES) {
+  if {[lsearch -exact $::env(ADDITIONAL_LIBS) $libFile] == -1} {
+    read_liberty $libFile
+  }
+}
+
+read_verilog results/asap7/mock-array_Element/base/6_final.v
+read_verilog $::env(RESULTS_DIR)/6_final.v
+read_verilog $::env(PLATFORM_DIR)/verilog/stdcell/empty.v
+
+link_design MockArray
+
+read_sdc $::env(RESULTS_DIR)/6_final.sdc
+read_spef $::env(RESULTS_DIR)/6_final.spef
+for {set x 0} {$x < 8} {incr x} {
+  for {set y 0} {$y < 8} {incr y} {
+    read_spef -path ces_${x}_${y} results/asap7/mock-array_Element/base/6_final.spef
+  }
+}
+
+report_parasitic_annotation
+report_power
+read_power_activities -scope TOP/MockArrayTestbench/postSynthesis -vcd designs/src/mock-array/MockArrayTestbench.vcd
+report_power

flow/designs/asap7/mock-array/simulate.sh

@@ -0,0 +1,20 @@
+#!/usr/bin/env bash
+set -ex
+
+# allow this script to be invoked from any folder
+DIR="$( cd "$( dirname "${BASH_SOURCE[0]}" )" && pwd )"
+BASE=$DIR/../..
+
+cd $DIR
+
+cd ../../src/mock-array
+cp ../../../results/asap7/mock-array/base/6_final.v post/MockArrayFinal.v
+cp ../../../results/asap7/mock-array_Element/base/6_final.v post/MockArrayElementFinal.v
+
+pwd
+rm -rf test_run_dir/
+sbt -Duser.home="$HOME" -Djline.terminal=jline.UnsupportedTerminal -batch \
+     "test:runMain SimulatePostSynthesis --width ${MOCK_ARRAY_COLS} --height ${MOCK_ARRAY_ROWS} --dataWidth ${MOCK_ARRAY_DATAWIDTH}"
+
+cp test_run_dir/MockArray_should_Wiggle_some_wires/MockArrayTestbench.vcd .
+

flow/designs/asap7/mock-array/verilog.sh

@@ -14,3 +14,8 @@ sbt -Duser.home="$HOME" -Djline.terminal=jline.UnsupportedTerminal -batch \
 
 # reduce git noise as these comments will change if the line numbers in Chisel changes
 find . -name "*.v" -type f -exec sed -i 's/ \/\/.*$//' {} \;
+
+sbt -Duser.home="$HOME" -Djline.terminal=jline.UnsupportedTerminal -batch \
+     "test:runMain GenerateMockArray --width ${MOCK_ARRAY_COLS} --height ${MOCK_ARRAY_ROWS} --dataWidth ${MOCK_ARRAY_DATAWIDTH} -- --emit-modules verilog --emission-options disableMemRandomization,disableRegisterRandomization --target-dir ."
+
+cp test_run_dir/MockArray_should_Wiggle_some_wires/MockArray.vcd .

flow/designs/src/mock-array/.gitignore

@@ -7,3 +7,4 @@ target/
 .bloop/
 .bsp/
 test_run_dir/
+MockArrayTestbench.vcd

flow/designs/src/mock-array/build.sbt

@@ -3,7 +3,7 @@ import scala.io.Source
 
 organization := "edu.berkeley.cs"
 
-scalaVersion := "2.13.6"
+scalaVersion := "2.13.10"
 
 scalacOptions ++= Seq("-deprecation", "-feature", "-unchecked", "-language:reflectiveCalls")
 

flow/designs/src/mock-array/post/.gitignore

@@ -0,0 +1 @@
+MockArray*.v

flow/designs/src/mock-array/src/main/scala/MockArray.scala

@@ -4,6 +4,10 @@
 import chisel3._
 
 import org.scalatest._
+import chiseltest._
+import chiseltest.simulator.SimulatorDebugAnnotation
+import chiseltest.simulator.VerilatorFlags
+import org.scalatest.flatspec.AnyFlatSpec
 
 import chisel3._
 import chisel3.util._
@@ -13,6 +17,7 @@ import scopt.OParser
 import System.err
 import scopt.RenderingMode
 import scala.collection.immutable.SeqMap
+import java.nio.file.Paths
 
 object Routes extends Enumeration {
   type Routes = Value
@@ -44,14 +49,15 @@ class BusesVec(singleElementWidth: Int, width: Int, height: Int)
   def asSeq: Seq[Vec[UInt]] = routes.map(_._2).toSeq
 }
 
+class MockArrayBundle(width: Int, height: Int, singleElementWidth: Int) extends Bundle {
+  val ins = Input(new BusesVec(singleElementWidth, width, height))
+  val outs = Output(new BusesVec(singleElementWidth, width, height))
+  val lsbs = Output(Vec(width * height, Bool()))
+}
+
 class MockArray(width: Int, height: Int, singleElementWidth: Int)
     extends Module {
-  val io = IO(new Bundle {
-    val ins = Input(new BusesVec(singleElementWidth, width, height))
-    val outs = Output(new BusesVec(singleElementWidth, width, height))
-
-    val lsbs = Output(Vec(width * height, Bool()))
-  })
+  val io = IO(new MockArrayBundle(width, height, singleElementWidth))
 
   class Element extends Module {
     val io =
@@ -147,49 +153,118 @@ case class ArrayConfig(
     remainingArgs: Seq[String] = Seq.empty
 )
 
-object GenerateMockArray extends App {
+class MockArrayPostSynthesis(width:Int, height:Int, singleElementWidth:Int) 
+extends BlackBox with HasBlackBoxPath {
+  override def desiredName = "MockArray"
+  val io = IO(new Bundle {
+    val clock = Input(Clock())
+    val reset = Input(Bool())
+    val io = new MockArrayBundle(width, height, singleElementWidth)
+  })
+  val platformDir = sys.env.getOrElse("PLATFORM_DIR", "defaultPath") + "/verilog/stdcell/"
+  (Seq("asap7sc7p5t_AO_RVT_TT_201020.v",
+    "dff.v",
+    "asap7sc7p5t_SIMPLE_RVT_TT_201020.v",
+    "asap7sc7p5t_INVBUF_RVT_TT_201020.v",
+    "empty.v").map(p=>Paths.get(platformDir + p)) ++
+    Seq(
+  "MockArrayFinal.v",
+  "MockArrayElementFinal.v").map(p=>Paths.get("post/" + p)))
+  .foreach(p=> addPath(p.toAbsolutePath().toString()))
+}
 
-  val builder = OParser.builder[ArrayConfig]
-  val parser = {
-    import builder._
-    OParser.sequence(
-      programName("my-program"),
-      opt[Int]('w', "width")
-        .required()
-        .valueName("Array width")
-        .action((width, c) => c.copy(width = width))
-        .text("input file is required"),
-      opt[Int]('h', "height")
-        .required()
-        .valueName("height")
-        .action((height, c) => c.copy(height = height))
-        .text("Array height"),
-      opt[Int]('d', "dataWidth")
-        .required()
-        .valueName("dataWidth")
-        .action((dataWidth, c) => c.copy(dataWidth = dataWidth))
-        .text("data path width")
-    )
+class MockArrayTestbench(width:Int, height:Int, singleElementWidth:Int) extends Module {
+  val io = IO(new MockArrayBundle(width, height, singleElementWidth))
+  val postSynthesis = Module(new MockArrayPostSynthesis(width, height, singleElementWidth))
+  postSynthesis.io.io <> io
+  postSynthesis.io.reset := reset.asBool
+  postSynthesis.io.clock := clock
+}
+
+
+class MockArrayTest(width:Int, height:Int, singleElementWidth:Int) extends AnyFlatSpec with ChiselScalatestTester {
+  behavior of "MockArray"
+
+  it should "Wiggle some wires" in {
+    // find full path foo.v in scala/src/resources
+    test(new MockArrayTestbench(width, height, singleElementWidth)).
+      withAnnotations(Seq(WriteVcdAnnotation,
+      VerilatorBackendAnnotation,
+      SimulatorDebugAnnotation,
+      // DD flip flops use UDP Tables, unsupported by Verilator
+      VerilatorFlags(Seq())
+      )) { dut =>
+      for (j <- 0 until 5) {
+        dut.io.ins.routes.foreach { case (route, vec) =>
+          vec.zipWithIndex.foreach { case (wire, i) =>
+            wire.poke((i+j).U)
+            dut.clock.step(1)
+          }
+        }
+      }
+    }
   }
+}
+
+
+object parse {
+  def apply(args:Array[String]) : (ArrayConfig, Array[String]) = {
+    val builder = OParser.builder[ArrayConfig]
+    val parser = {
+      import builder._
+      OParser.sequence(
+        programName("my-program"),
+        opt[Int]('w', "width")
+          .required()
+          .valueName("Array width")
+          .action((width, c) => c.copy(width = width))
+          .text("input file is required"),
+        opt[Int]('h', "height")
+          .required()
+          .valueName("height")
+          .action((height, c) => c.copy(height = height))
+          .text("Array height"),
+        opt[Int]('d', "dataWidth")
+          .required()
+          .valueName("dataWidth")
+          .action((dataWidth, c) => c.copy(dataWidth = dataWidth))
+          .text("data path width")
+      )
+    }
+
+    val (configArgs, afterDelimiter) = args.span(_ != "--")
+    val chiselArgs = afterDelimiter.drop(1)
 
-  val (configArgs, afterDelimiter) = args.span(_ != "--")
-  val chiselArgs = afterDelimiter.drop(1)
-
-  OParser.parse(parser, configArgs, ArrayConfig()) match {
-    case Some(c) =>
-      new ChiselStage()
-        .execute(
-          chiselArgs,
-          Seq(
-            ChiselGeneratorAnnotation(() =>
-              new MockArray(c.width, c.height, c.dataWidth)
-            )
-          )
-        )
 
-    case _ =>
-      // arguments are invalid
-      OParser.usage(parser, RenderingMode.TwoColumns)
-      sys.exit(1)
+
+    OParser.parse(parser, configArgs, ArrayConfig()) match {
+      case Some(c) =>
+        return (c, chiselArgs)
+
+      case _ =>
+        // arguments are invalid
+        OParser.usage(parser, RenderingMode.TwoColumns)
+        sys.exit(1)
+    }
   }
+
+}
+
+object GenerateMockArray extends App {
+  val (c, chiselArgs) = parse(args)
+
+  new ChiselStage()
+    .execute(
+      chiselArgs,
+      Seq(
+        ChiselGeneratorAnnotation(() =>
+          new MockArray(c.width, c.height, c.dataWidth)
+        )
+      )
+    )
+}
+
+object SimulatePostSynthesis extends App {
+  val (c, chiselArgs) = parse(args)
+  new MockArrayTest(c.width, c.height, c.dataWidth).execute()
 }

flow/platforms/asap7/verilog/stdcell/README.md

@@ -0,0 +1,15 @@
+ASAP7 behavioral model files
+============================
+
+These are unmodified files from
+https://github.com/The-OpenROAD-Project/asap7sc7p5t_28/tree/main/Verilog
+
+Note that some tools, notably Verilator, might struggle with some
+of the SystemVerilog features used by the behavioral logic files in
+the ASAP7 PDK.
+
+To work around this ORFS re-implements some behavioral such as the dff.v
+and empty.v to allow for post-synthesis simulation to use OpenSTA
+read_power_activities features.
+
+