We read every piece of feedback, and take your input very seriously.
To see all available qualifiers, see our documentation.
There was an error while loading. Please reload this page.
2 parents 4ad47a4 + 61cac7d commit 7894b1aCopy full SHA for 7894b1a
flow/scripts/floorplan.tcl
@@ -2,6 +2,12 @@ utl::set_metrics_stage "floorplan__{}"
2
source $::env(SCRIPTS_DIR)/load.tcl
3
load_design 1_synth.v 1_synth.sdc "Starting floorplan"
4
5
+#Run check_setup
6
+puts "\n=========================================================================="
7
+puts "Floorplan check_setup"
8
+puts "--------------------------------------------------------------------------"
9
+check_setup
10
+
11
set num_instances [llength [get_cells -hier *]]
12
puts "number instances in verilog is $num_instances"
13
0 commit comments