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malibertymaliberty
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Merge pull request #785 from vijayank88/arian136_add
ariane136 added for Nangate45 platform
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‎flow/Makefile‎

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# ==============================================================================
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# DESIGN_CONFIG=./designs/nangate45/aes/config.mk
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# DESIGN_CONFIG=./designs/nangate45/ariane136/config.mk
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# DESIGN_CONFIG=./designs/nangate45/black_parrot/config.mk
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# DESIGN_CONFIG=./designs/nangate45/bp_be_top/config.mk
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# DESIGN_CONFIG=./designs/nangate45/bp_fe_top/config.mk

‎flow/designs/nangate45/ariane136/config.mk‎

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export DESIGN_NAME = ariane
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export DESIGN_NICKNAME = ariane136
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export PLATFORM = nangate45
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export SYNTH_HIERARCHICAL = 1
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export MAX_UNGROUP_SIZE ?= 1000
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export RTLMP_FLOW = True
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# RTL_MP Settings
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export RTLMP_MAX_INST = 500000
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export RTLMP_MIN_INST = 1000
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export RTLMP_MAX_MACRO = 140
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export RTLMP_MIN_MACRO = 4
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export VERILOG_FILES = ./designs/src/$(DESIGN_NICKNAME)/ariane.sv2v.v \
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./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/macros.v
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export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc
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export ADDITIONAL_LEFS = $(PLATFORM_DIR)/lef/fakeram45_256x16.lef
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export ADDITIONAL_LIBS = $(PLATFORM_DIR)/lib/fakeram45_256x16.lib
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export DIE_AREA = 0 0 1500 1500
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export CORE_AREA = 10 12 1448 1448
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export MACRO_PLACE_HALO = 15 15
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export MACRO_PLACE_CHANNEL = 15 15

‎flow/designs/nangate45/ariane136/constraint.sdc‎

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‎flow/designs/nangate45/ariane136/macros.v‎

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module SyncSpRamBeNx64_00000008_00000100_0_2
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(
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Clk_CI,
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Rst_RBI,
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CSel_SI,
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WrEn_SI,
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BEn_SI,
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WrData_DI,
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Addr_DI,
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RdData_DO
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);
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input [7:0] BEn_SI; // byte-enable: ignore or use as needed
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input [63:0] WrData_DI;
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input [7:0] Addr_DI;
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output [63:0] RdData_DO;
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input Clk_CI;
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input Rst_RBI; // reset: ignore or use as needed
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input CSel_SI;
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input WrEn_SI;
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wire [63:0] RdData_DO;
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wire csel_b,wren_b;
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wire [15:0] WMaskIn, NotWMaskIn;
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assign NotWMaskIn = 16'b0;
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assign WMaskIn = ~NotWMaskIn;
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assign wren_b = ~WrEn_SI; // active-low global-write-enable
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assign csel_b = ~CSel_SI; // active-low chip-select-enable
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fakeram45_256x16 macro_mem_0 (.clk(Clk_CI),.rd_out(RdData_DO[15:0]), .ce_in(csel_b),.we_in(wren_b),.addr_in(Addr_DI),.w_mask_in(WMaskIn),.wd_in(WrData_DI[15:0]));
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fakeram45_256x16 macro_mem_1 (.clk(Clk_CI),.rd_out(RdData_DO[31:16]),.ce_in(csel_b),.we_in(wren_b),.addr_in(Addr_DI),.w_mask_in(WMaskIn),.wd_in(WrData_DI[31:16]));
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fakeram45_256x16 macro_mem_2 (.clk(Clk_CI),.rd_out(RdData_DO[47:32]),.ce_in(csel_b),.we_in(wren_b),.addr_in(Addr_DI),.w_mask_in(WMaskIn),.wd_in(WrData_DI[47:32]));
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fakeram45_256x16 macro_mem_3 (.clk(Clk_CI),.rd_out(RdData_DO[63:48]),.ce_in(csel_b),.we_in(wren_b),.addr_in(Addr_DI),.w_mask_in(WMaskIn),.wd_in(WrData_DI[63:48]));
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endmodule // SyncSpRamBeNx64_00000008_00000100_0_2
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// Google made a mistake in their ariane experiment.
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// The valid_dirty_sram should be 4 macros, each 256x16. Instead, they only instantiated 1 256x16 macro
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module limping_SyncSpRamBeNx64_00000008_00000100_0_2
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(
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Clk_CI,
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Rst_RBI,
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CSel_SI,
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WrEn_SI,
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BEn_SI,
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WrData_DI,
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Addr_DI,
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RdData_DO
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);
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input [7:0] BEn_SI; // byte-enable: ignore or use as needed
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input [63:0] WrData_DI;
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input [7:0] Addr_DI;
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output [63:0] RdData_DO;
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input Clk_CI;
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input Rst_RBI; // reset: ignore or use as needed
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input CSel_SI;
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input WrEn_SI;
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wire [63:0] RdData_DO;
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wire csel_b,wren_b;
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wire [15:0] WMaskIn, NotWMaskIn;
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assign NotWMaskIn = 16'b0;
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assign WMaskIn = ~NotWMaskIn;
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assign wren_b = ~WrEn_SI; // active-low global-write-enable
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assign csel_b = ~CSel_SI; // active-low chip-select-enable
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fakeram45_256x16 macro_mem_0 (.clk(Clk_CI),.rd_out(RdData_DO[15:0]), .ce_in(csel_b),.we_in(wren_b),.addr_in(Addr_DI),.w_mask_in(WMaskIn),.wd_in(WrData_DI[15:0]));
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fakeram45_256x16 macro_mem_1 (.clk(Clk_CI),.rd_out(RdData_DO[31:16]),.ce_in(csel_b),.we_in(wren_b),.addr_in(Addr_DI),.w_mask_in(WMaskIn),.wd_in(WrData_DI[31:16]));
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fakeram45_256x16 macro_mem_2 (.clk(Clk_CI),.rd_out(RdData_DO[47:32]),.ce_in(csel_b),.we_in(wren_b),.addr_in(Addr_DI),.w_mask_in(WMaskIn),.wd_in(WrData_DI[47:32]));
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fakeram45_256x16 macro_mem_3 (.clk(Clk_CI),.rd_out(RdData_DO[63:48]),.ce_in(csel_b),.we_in(wren_b),.addr_in(Addr_DI),.w_mask_in(WMaskIn),.wd_in(WrData_DI[63:48]));
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endmodule // limping_SyncSpRamBeNx64_00000008_00000100_0_2
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module SyncSpRamBeNx64_00000008_00000100_0_2_d45
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(
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Clk_CI,
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Rst_RBI,
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CSel_SI,
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WrEn_SI,
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BEn_SI,
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WrData_DI,
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Addr_DI,
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RdData_DO
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);
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input [7:0] BEn_SI; // byte-enable: ignore or use as needed
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input [44:0] WrData_DI;
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input [7:0] Addr_DI;
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output [44:0] RdData_DO;
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input Clk_CI;
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input Rst_RBI; // reset: ignore or use as needed
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input CSel_SI;
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input WrEn_SI;
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wire [47:0] RdData_DO_wire;
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wire csel_b,wren_b;
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wire [15:0] WMaskIn, NotWMaskIn;
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assign NotWMaskIn = 16'b0;
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assign WMaskIn = ~NotWMaskIn;
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assign wren_b = ~WrEn_SI; // active-low global-write-enable
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assign csel_b = ~CSel_SI; // active-low chip-select-enable
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assign RdData_DO = RdData_DO_wire[44:0];
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fakeram45_256x16 macro_mem_0 (.clk(Clk_CI),.rd_out(RdData_DO_wire[15:0]), .ce_in(csel_b),.we_in(wren_b),.addr_in(Addr_DI),.w_mask_in(WMaskIn),.wd_in(WrData_DI[15:0]));
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fakeram45_256x16 macro_mem_1 (.clk(Clk_CI),.rd_out(RdData_DO_wire[31:16]),.ce_in(csel_b),.we_in(wren_b),.addr_in(Addr_DI),.w_mask_in(WMaskIn),.wd_in(WrData_DI[31:16]));
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fakeram45_256x16 macro_mem_2 (.clk(Clk_CI),.rd_out(RdData_DO_wire[47:32]),.ce_in(csel_b),.we_in(wren_b),.addr_in(Addr_DI),.w_mask_in(WMaskIn),.wd_in({3'b000, WrData_DI[44:32]}));
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endmodule // SyncSpRamBeNx64_00000008_00000100_0_2_d45
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module SyncSpRamBeNx64_00000008_00000100_0_2_d44
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(
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Clk_CI,
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Rst_RBI,
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CSel_SI,
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WrEn_SI,
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BEn_SI,
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WrData_DI,
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Addr_DI,
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RdData_DO
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);
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input [7:0] BEn_SI; // byte-enable: ignore or use as needed
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input [43:0] WrData_DI;
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input [7:0] Addr_DI;
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output [43:0] RdData_DO;
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input Clk_CI;
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input Rst_RBI; // reset: ignore or use as needed
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input CSel_SI;
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input WrEn_SI;
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wire [47:0] RdData_DO_wire;
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wire csel_b,wren_b;
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wire [15:0] WMaskIn, NotWMaskIn;
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assign NotWMaskIn = 16'b0;
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assign WMaskIn = ~NotWMaskIn;
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assign wren_b = ~WrEn_SI; // active-low global-write-enable
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assign csel_b = ~CSel_SI; // active-low chip-select-enable
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assign RdData_DO = RdData_DO_wire[43:0];
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fakeram45_256x16 macro_mem_0 (.clk(Clk_CI),.rd_out(RdData_DO_wire[15:0]), .ce_in(csel_b),.we_in(wren_b),.addr_in(Addr_DI),.w_mask_in(WMaskIn),.wd_in(WrData_DI[15:0]));
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fakeram45_256x16 macro_mem_1 (.clk(Clk_CI),.rd_out(RdData_DO_wire[31:16]),.ce_in(csel_b),.we_in(wren_b),.addr_in(Addr_DI),.w_mask_in(WMaskIn),.wd_in(WrData_DI[31:16]));
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fakeram45_256x16 macro_mem_2 (.clk(Clk_CI),.rd_out(RdData_DO_wire[47:32]),.ce_in(csel_b),.we_in(wren_b),.addr_in(Addr_DI),.w_mask_in(WMaskIn),.wd_in({4'b0000, WrData_DI[43:32]}));
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endmodule // SyncSpRamBeNx64_00000008_00000100_0_2_d44

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