ci: metrics fix

nangate45/gcd base
[INFO] Tightening rule synth__design__instance__area__stdcell from 55557.26 to 597.73.
[INFO] Tightening rule placeopt__design__instance__area from 60306 to 622.
[INFO] Tightening rule placeopt__design__instance__count__stdcell from 29637 to 508.
[INFO] Updating failing rule globalroute__timing__clock__slack from 0.0 to -0.1.
[INFO] Updating failing rule globalroute__timing__setup__ws from 0.0 to -0.1.
[INFO] Tightening rule detailedroute__route__wirelength from 669467 to 2936.
[INFO] Updating failing rule finish__timing__setup__ws from 0.0 to -0.09.
[INFO] Tightening rule finish__design__instance__area from 60640 to 697.
[INFO] Updating failing rule finish__timing__drv__setup_violation_count from 10 to 32.
[INFO] Updating failing rule finish__timing__wns_percent_delay from -10.0 to -30.69.

asap7/sha3 base
[INFO] Updating failing rule finish__timing__drv__setup_violation_count from 10 to 48.
[INFO] Updating failing rule finish__timing__drv__hold_violation_count from 10 to 27.

nangate45/swerv base
[INFO] Updating failing rule synth__design__instance__area__stdcell from 55557.26 to 176767.07.
[INFO] Updating failing rule placeopt__design__instance__area from 60306 to 200286.
[INFO] Updating failing rule placeopt__design__instance__count__stdcell from 29637 to 94699.
[INFO] Updating failing rule detailedroute__route__wirelength from 669467 to 2693259.
[INFO] Updating failing rule finish__design__instance__area from 60640 to 201204.
[INFO] Updating failing rule finish__timing__drv__max_slew_limit from -0.2 to -0.47.
[INFO] Updating failing rule finish__timing__drv__max_cap_limit from -0.24 to -1.64.
[INFO] Updating failing rule finish__timing__drv__hold_violation_count from 10 to 293.

nangate45/swerv_wrapper base
[INFO] Updating failing rule synth__design__instance__area__stdcell from 55557.26 to 735404.71.
[INFO] Updating failing rule placeopt__design__instance__area from 60306 to 771530.
[INFO] Updating failing rule placeopt__design__instance__count__stdcell from 29637 to 110360.
[INFO] Updating failing rule detailedroute__route__wirelength from 669467 to 4605000.
[INFO] Updating failing rule finish__timing__setup__ws from 0.0 to -0.31.
[INFO] Updating failing rule finish__design__instance__area from 60640 to 772515.
[INFO] Updating failing rule finish__timing__drv__max_cap_limit from -0.24 to -0.61.
[INFO] Updating failing rule finish__timing__drv__setup_violation_count from 10 to 240.

Signed-off-by: Vitor Bandeira <[email protected]>

Author: vvbandeira

flow/designs/asap7/sha3/metadata-base-ok.json

@@ -9,6 +9,7 @@
   "cts__clock__skew__setup": 7.54394,
   "cts__clock__skew__setup__post_repair": 8.76758,
   "cts__clock__skew__setup__pre_repair": 8.76758,
+  "cts__cpu__total": 34.74,
   "cts__design__core__area": 5597.58,
   "cts__design__core__area__post_repair": 5597.58,
   "cts__design__core__area__pre_repair": 5597.58,
@@ -25,13 +26,13 @@
   "cts__design__instance__area__stdcell__post_repair": 2171.14,
   "cts__design__instance__area__stdcell__pre_repair": 2171.14,
   "cts__design__instance__count": 17245,
-  "cts__design__instance__count__hold_buffer": 78.0,
+  "cts__design__instance__count__hold_buffer": 78,
   "cts__design__instance__count__macros": 0,
   "cts__design__instance__count__macros__post_repair": 0,
   "cts__design__instance__count__macros__pre_repair": 0,
   "cts__design__instance__count__post_repair": 17082,
   "cts__design__instance__count__pre_repair": 17082,
-  "cts__design__instance__count__setup_buffer": 85.0,
+  "cts__design__instance__count__setup_buffer": 85,
   "cts__design__instance__count__stdcell": 17245,
   "cts__design__instance__count__stdcell__post_repair": 17082,
   "cts__design__instance__count__stdcell__pre_repair": 17082,
@@ -48,7 +49,21 @@
   "cts__design__io__post_repair": 76,
   "cts__design__io__pre_repair": 76,
   "cts__design__violations": 0,
+  "cts__mem__peak": 268344.0,
+  "cts__power__internal__total": 0.0171426,
+  "cts__power__internal__total__post_repair": 0.0171114,
+  "cts__power__internal__total__pre_repair": 0.0171114,
+  "cts__power__leakage__total": 2.04759e-06,
+  "cts__power__leakage__total__post_repair": 2.02213e-06,
+  "cts__power__leakage__total__pre_repair": 2.02213e-06,
+  "cts__power__switching__total": 0.0119483,
+  "cts__power__switching__total__post_repair": 0.0118704,
+  "cts__power__switching__total__pre_repair": 0.0118704,
+  "cts__power__total": 0.0290929,
+  "cts__power__total__post_repair": 0.0289838,
+  "cts__power__total__pre_repair": 0.0289838,
   "cts__route__wirelength__estimated": 44698.7,
+  "cts__runtime__total": "0:34.91",
   "cts__timing__drv__hold_violation_count": 0,
   "cts__timing__drv__hold_violation_count__post_repair": 1161,
   "cts__timing__drv__hold_violation_count__pre_repair": 1161,
@@ -79,7 +94,10 @@
   "cts__timing__setup__ws": -40.8013,
   "cts__timing__setup__ws__post_repair": -348.811,
   "cts__timing__setup__ws__pre_repair": -348.811,
-  "detailedplace__cpu__total": 12.23,
+  "cts_fill__cpu__total": 2.22,
+  "cts_fill__mem__peak": 216860.0,
+  "cts_fill__runtime__total": "0:02.37",
+  "detailedplace__cpu__total": 12.3,
   "detailedplace__design__core__area": 5597.58,
   "detailedplace__design__die__area": 8100,
   "detailedplace__design__instance__area": 2161.44,
@@ -95,9 +113,13 @@
   "detailedplace__design__instance__utilization__stdcell": 0.386138,
   "detailedplace__design__io": 76,
   "detailedplace__design__violations": 0,
-  "detailedplace__mem__peak": 245084.0,
+  "detailedplace__mem__peak": 250440.0,
+  "detailedplace__power__internal__total": 0.0169408,
+  "detailedplace__power__leakage__total": 2.00768e-06,
+  "detailedplace__power__switching__total": 0.00996507,
+  "detailedplace__power__total": 0.0269078,
   "detailedplace__route__wirelength__estimated": 42472.6,
-  "detailedplace__runtime__total": "0:12.41",
+  "detailedplace__runtime__total": "0:12.47",
   "detailedplace__timing__drv__hold_violation_count": 0,
   "detailedplace__timing__drv__max_cap": 0,
   "detailedplace__timing__drv__max_cap_limit": 0.126303,
@@ -108,6 +130,8 @@
   "detailedplace__timing__drv__setup_violation_count": 32,
   "detailedplace__timing__setup__tns": -10310.6,
   "detailedplace__timing__setup__ws": -348.811,
+  "detailedroute__cpu__total": 3693.35,
+  "detailedroute__mem__peak": 4963472.0,
   "detailedroute__route__drc_errors": 0,
   "detailedroute__route__drc_errors__iter:1": 10127,
   "detailedroute__route__drc_errors__iter:2": 570,
@@ -125,9 +149,10 @@
   "detailedroute__route__wirelength__iter:3": 61561,
   "detailedroute__route__wirelength__iter:4": 61562,
   "detailedroute__route__wirelength__iter:5": 61561,
+  "detailedroute__runtime__total": "4:20.86",
   "finish__clock__skew__hold": 12.464,
   "finish__clock__skew__setup": 11.7733,
-  "finish__cpu__total": 41.73,
+  "finish__cpu__total": 40.09,
   "finish__design__core__area": 5597.58,
   "finish__design__die__area": 8100,
   "finish__design__instance__area": 2187.87,
@@ -139,20 +164,27 @@
   "finish__design__instance__utilization": 0.390861,
   "finish__design__instance__utilization__stdcell": 0.390861,
   "finish__design__io": 76,
-  "finish__mem__peak": 1343200.0,
-  "finish__runtime__total": "0:42.11",
-  "finish__timing__drv__hold_violation_count": 1.0,
+  "finish__mem__peak": 1344840.0,
+  "finish__power__internal__total": 0.0171974,
+  "finish__power__leakage__total": 2.04759e-06,
+  "finish__power__switching__total": 0.012143,
+  "finish__power__total": 0.0293425,
+  "finish__runtime__total": "0:40.43",
+  "finish__timing__drv__hold_violation_count": 14,
   "finish__timing__drv__max_cap": 0,
   "finish__timing__drv__max_cap_limit": 0.139246,
   "finish__timing__drv__max_fanout": 0,
   "finish__timing__drv__max_fanout_limit": 0,
   "finish__timing__drv__max_slew": 174,
   "finish__timing__drv__max_slew_limit": -0.258697,
-  "finish__timing__drv__setup_violation_count": 1.0,
+  "finish__timing__drv__setup_violation_count": 32,
   "finish__timing__setup__tns": -2342.28,
   "finish__timing__setup__ws": -102.713,
   "finish__timing__wns_percent_delay": -16.208152,
-  "floorplan__cpu__total": 2.18,
+  "finish_merge__cpu__total": 3.93,
+  "finish_merge__mem__peak": 378612.0,
+  "finish_merge__runtime__total": "0:04.93",
+  "floorplan__cpu__total": 6.16,
   "floorplan__design__core__area": 5597.58,
   "floorplan__design__die__area": 8100,
   "floorplan__design__instance__area": 1982.6,
@@ -164,11 +196,30 @@
   "floorplan__design__instance__utilization": 0.354189,
   "floorplan__design__instance__utilization__stdcell": 0.354189,
   "floorplan__design__io": 76,
-  "floorplan__mem__peak": 182052.0,
-  "floorplan__runtime__total": "0:02.29",
+  "floorplan__mem__peak": 223948.0,
+  "floorplan__power__internal__total": 0.0191355,
+  "floorplan__power__leakage__total": 1.78854e-06,
+  "floorplan__power__switching__total": 0.00759428,
+  "floorplan__power__total": 0.0267315,
+  "floorplan__runtime__total": "0:06.46",
   "floorplan__timing__setup__tns": -6700830.0,
   "floorplan__timing__setup__ws": -7935.57,
-  "globalplace__cpu__total": 20.05,
+  "floorplan_io__cpu__total": 1.96,
+  "floorplan_io__mem__peak": 185216.0,
+  "floorplan_io__runtime__total": "0:02.07",
+  "floorplan_macro__cpu__total": 1.94,
+  "floorplan_macro__mem__peak": 184012.0,
+  "floorplan_macro__runtime__total": "0:02.03",
+  "floorplan_pdn__cpu__total": 2.13,
+  "floorplan_pdn__mem__peak": 187328.0,
+  "floorplan_pdn__runtime__total": "0:02.24",
+  "floorplan_tap__cpu__total": 1.9,
+  "floorplan_tap__mem__peak": 175468.0,
+  "floorplan_tap__runtime__total": "0:02.00",
+  "floorplan_tdms__cpu__total": 1.93,
+  "floorplan_tdms__mem__peak": 184136.0,
+  "floorplan_tdms__runtime__total": "0:02.04",
+  "globalplace__cpu__total": 61.53,
   "globalplace__design__core__area": 5597.58,
   "globalplace__design__die__area": 8100,
   "globalplace__design__instance__area": 2006.89,
@@ -180,14 +231,25 @@
   "globalplace__design__instance__utilization": 0.358529,
   "globalplace__design__instance__utilization__stdcell": 0.358529,
   "globalplace__design__io": 76,
-  "globalplace__mem__peak": 259128.0,
-  "globalplace__runtime__total": "0:20.23",
+  "globalplace__mem__peak": 402384.0,
+  "globalplace__power__internal__total": 0.0231132,
+  "globalplace__power__leakage__total": 1.78854e-06,
+  "globalplace__power__switching__total": 0.0091704,
+  "globalplace__power__total": 0.0322854,
+  "globalplace__runtime__total": "1:01.75",
   "globalplace__timing__setup__tns": -13549600.0,
   "globalplace__timing__setup__ws": -14128.3,
+  "globalplace_io__cpu__total": 2.06,
+  "globalplace_io__mem__peak": 187012.0,
+  "globalplace_io__runtime__total": "0:02.16",
+  "globalplace_skip_io__cpu__total": 6.61,
+  "globalplace_skip_io__mem__peak": 206684.0,
+  "globalplace_skip_io__runtime__total": "0:06.74",
   "globalroute__antenna__violating__nets": 0,
   "globalroute__antenna__violating__pins": 0,
   "globalroute__clock__skew__hold": 9.61149,
   "globalroute__clock__skew__setup": 9.61149,
+  "globalroute__cpu__total": 12.27,
   "globalroute__design__core__area": 5597.58,
   "globalroute__design__die__area": 8100,
   "globalroute__design__instance__area": 2187.87,
@@ -199,6 +261,12 @@
   "globalroute__design__instance__utilization": 0.390861,
   "globalroute__design__instance__utilization__stdcell": 0.390861,
   "globalroute__design__io": 76,
+  "globalroute__mem__peak": 484844.0,
+  "globalroute__power__internal__total": 0.017169,
+  "globalroute__power__leakage__total": 2.04759e-06,
+  "globalroute__power__switching__total": 0.0125899,
+  "globalroute__power__total": 0.029761,
+  "globalroute__runtime__total": "0:12.58",
   "globalroute__timing__clock__slack": -55.808,
   "globalroute__timing__drv__hold_violation_count": 3,
   "globalroute__timing__drv__max_cap": 0,
@@ -210,7 +278,7 @@
   "globalroute__timing__drv__setup_violation_count": 14,
   "globalroute__timing__setup__tns": -223.857,
   "globalroute__timing__setup__ws": -55.8082,
-  "placeopt__cpu__total": 20.05,
+  "placeopt__cpu__total": 21.37,
   "placeopt__design__core__area": 5597.58,
   "placeopt__design__core__area__pre_opt": 5597.58,
   "placeopt__design__die__area": 8100,
@@ -233,8 +301,16 @@
   "placeopt__design__instance__utilization__stdcell__pre_opt": 0.358529,
   "placeopt__design__io": 76,
   "placeopt__design__io__pre_opt": 76,
-  "placeopt__mem__peak": 259128.0,
-  "placeopt__runtime__total": "0:20.23",
+  "placeopt__mem__peak": 264412.0,
+  "placeopt__power__internal__total": 0.0169313,
+  "placeopt__power__internal__total__pre_opt": 0.0230081,
+  "placeopt__power__leakage__total": 2.00768e-06,
+  "placeopt__power__leakage__total__pre_opt": 1.78854e-06,
+  "placeopt__power__switching__total": 0.00991345,
+  "placeopt__power__switching__total__pre_opt": 0.0091704,
+  "placeopt__power__total": 0.0268468,
+  "placeopt__power__total__pre_opt": 0.0321803,
+  "placeopt__runtime__total": "0:21.54",
   "placeopt__timing__drv__hold_violation_count": 0,
   "placeopt__timing__drv__max_cap": 0,
   "placeopt__timing__drv__max_cap_limit": 0.109528,
@@ -248,10 +324,10 @@
   "placeopt__timing__setup__ws": -360.043,
   "placeopt__timing__setup__ws__pre_opt": -14128.3,
   "run__flow__design": "sha3",
-  "run__flow__generate_date": "2023-06-20 07:29",
+  "run__flow__generate_date": "2023-07-17 14:06",
   "run__flow__metrics_version": "Metrics_2.1.2",
   "run__flow__openroad_commit": "N/A",
-  "run__flow__openroad_version": "v2.0-8774-gaed70e329",
+  "run__flow__openroad_version": "v2.0-9070-gbb341ffb9",
   "run__flow__platform": "asap7",
   "run__flow__platform__capacitance_units": "1fF",
   "run__flow__platform__current_units": "1mA",
@@ -260,14 +336,14 @@
   "run__flow__platform__resistance_units": "1kohm",
   "run__flow__platform__time_units": "1ps",
   "run__flow__platform__voltage_units": "1v",
-  "run__flow__platform_commit": "8cdd51fb3fc6462a3892efe81b1007503b7ce14a",
-  "run__flow__scripts_commit": "8cdd51fb3fc6462a3892efe81b1007503b7ce14a",
-  "run__flow__uuid": "8a4f4fda-aa8b-481a-911f-31d93a0ce24d",
+  "run__flow__platform_commit": "71aa303a8500be564c6a643f10fe2ec1254aab4f",
+  "run__flow__scripts_commit": "71aa303a8500be564c6a643f10fe2ec1254aab4f",
+  "run__flow__uuid": "afc4f190-f76d-4b9c-b384-bfb916126419",
   "run__flow__variant": "base",
-  "synth__cpu__total": 47.42,
+  "synth__cpu__total": 43.29,
   "synth__design__instance__area__stdcell": 2078.61228,
   "synth__design__instance__count__stdcell": 16118.0,
-  "synth__mem__peak": 139364.0,
-  "synth__runtime__total": "0:49.12",
-  "total_time": "0:02:26.390000"
+  "synth__mem__peak": 138352.0,
+  "synth__runtime__total": "0:45.18",
+  "total_time": "0:08:42.760000"
 }

flow/designs/asap7/sha3/rules-base.json

@@ -76,11 +76,11 @@
         "compare": ">="
     },
     "finish__timing__drv__setup_violation_count": {
-        "value": 10,
+        "value": 48,
         "compare": "<="
     },
     "finish__timing__drv__hold_violation_count": {
-        "value": 10,
+        "value": 27,
         "compare": "<="
     },
     "finish__timing__wns_percent_delay": {