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Use glob pattern in Ibex configs
Signed-off-by: Martin Povišer <[email protected]>
1 parent c4a1f28 commit 871cff4

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8 files changed

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-160
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8 files changed

+8
-160
lines changed

‎flow/designs/asap7/ibex/config.mk‎

Lines changed: 1 addition & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -3,26 +3,7 @@ export PLATFORM = asap7
33
export DESIGN_NICKNAME = ibex
44
export DESIGN_NAME = ibex_core
55

6-
export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_pkg.sv \
7-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_alu.sv \
8-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_compressed_decoder.sv \
9-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_controller.sv \
10-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_cs_registers.sv \
11-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_counter.sv \
12-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_decoder.sv \
13-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_ex_block.sv \
14-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_id_stage.sv \
15-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_if_stage.sv \
16-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_wb_stage.sv \
17-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_load_store_unit.sv \
18-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_multdiv_slow.sv \
19-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_multdiv_fast.sv \
20-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_prefetch_buffer.sv \
21-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_fetch_fifo.sv \
22-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_pmp.sv \
23-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_csr.sv \
24-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_core.sv \
25-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_register_file_ff.sv \
6+
export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.sv)) \
267
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/syn/rtl/prim_clock_gating.v
278

289
export VERILOG_INCLUDE_DIRS = \

‎flow/designs/gf12/ibex/config.mk‎

Lines changed: 1 addition & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -2,26 +2,7 @@ export DESIGN_NICKNAME = ibex
22
export DESIGN_NAME = ibex_core
33
export PLATFORM = gf12
44

5-
export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_pkg.sv \
6-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_alu.sv \
7-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_compressed_decoder.sv \
8-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_controller.sv \
9-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_cs_registers.sv \
10-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_counter.sv \
11-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_decoder.sv \
12-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_ex_block.sv \
13-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_id_stage.sv \
14-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_if_stage.sv \
15-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_wb_stage.sv \
16-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_load_store_unit.sv \
17-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_multdiv_slow.sv \
18-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_multdiv_fast.sv \
19-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_prefetch_buffer.sv \
20-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_fetch_fifo.sv \
21-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_pmp.sv \
22-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_csr.sv \
23-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_core.sv \
24-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_register_file_ff.sv \
5+
export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.sv)) \
256
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/syn/rtl/prim_clock_gating.v
267

278
export VERILOG_INCLUDE_DIRS = \

‎flow/designs/gf180/ibex/config.mk‎

Lines changed: 1 addition & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -2,26 +2,7 @@ export DESIGN_NICKNAME = ibex
22
export DESIGN_NAME = ibex_core
33
export PLATFORM = gf180
44

5-
export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_pkg.sv \
6-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_alu.sv \
7-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_compressed_decoder.sv \
8-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_controller.sv \
9-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_cs_registers.sv \
10-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_counter.sv \
11-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_decoder.sv \
12-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_ex_block.sv \
13-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_id_stage.sv \
14-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_if_stage.sv \
15-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_wb_stage.sv \
16-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_load_store_unit.sv \
17-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_multdiv_slow.sv \
18-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_multdiv_fast.sv \
19-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_prefetch_buffer.sv \
20-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_fetch_fifo.sv \
21-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_pmp.sv \
22-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_csr.sv \
23-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_core.sv \
24-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_register_file_ff.sv \
5+
export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.sv)) \
256
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/syn/rtl/prim_clock_gating.v
267

278
export VERILOG_INCLUDE_DIRS = \

‎flow/designs/ihp-sg13g2/ibex/config.mk‎

Lines changed: 1 addition & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -2,26 +2,7 @@ export DESIGN_NICKNAME = ibex
22
export DESIGN_NAME = ibex_core
33
export PLATFORM = ihp-sg13g2
44

5-
export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_pkg.sv \
6-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_alu.sv \
7-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_compressed_decoder.sv \
8-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_controller.sv \
9-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_cs_registers.sv \
10-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_counter.sv \
11-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_decoder.sv \
12-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_ex_block.sv \
13-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_id_stage.sv \
14-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_if_stage.sv \
15-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_wb_stage.sv \
16-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_load_store_unit.sv \
17-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_multdiv_slow.sv \
18-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_multdiv_fast.sv \
19-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_prefetch_buffer.sv \
20-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_fetch_fifo.sv \
21-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_pmp.sv \
22-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_csr.sv \
23-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_core.sv \
24-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_register_file_ff.sv \
5+
export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.sv)) \
256
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/syn/rtl/prim_clock_gating.v
267

278
export VERILOG_INCLUDE_DIRS = \

‎flow/designs/intel16/ibex/config.mk‎

Lines changed: 1 addition & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -4,26 +4,7 @@ export DESIGN_NICKNAME = ibex
44
export DESIGN_NAME = ibex_core
55
export PLATFORM = intel16
66

7-
export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_pkg.sv \
8-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_alu.sv \
9-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_compressed_decoder.sv \
10-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_controller.sv \
11-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_cs_registers.sv \
12-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_counter.sv \
13-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_decoder.sv \
14-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_ex_block.sv \
15-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_id_stage.sv \
16-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_if_stage.sv \
17-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_wb_stage.sv \
18-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_load_store_unit.sv \
19-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_multdiv_slow.sv \
20-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_multdiv_fast.sv \
21-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_prefetch_buffer.sv \
22-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_fetch_fifo.sv \
23-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_pmp.sv \
24-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_csr.sv \
25-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_core.sv \
26-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_register_file_ff.sv \
7+
export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.sv)) \
278
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/syn/rtl/prim_clock_gating.v
289

2910
export VERILOG_INCLUDE_DIRS = \

‎flow/designs/nangate45/ibex/config.mk‎

Lines changed: 1 addition & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -2,26 +2,7 @@ export DESIGN_NICKNAME = ibex
22
export DESIGN_NAME = ibex_core
33
export PLATFORM = nangate45
44

5-
export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_pkg.sv \
6-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_alu.sv \
7-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_compressed_decoder.sv \
8-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_controller.sv \
9-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_cs_registers.sv \
10-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_counter.sv \
11-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_decoder.sv \
12-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_ex_block.sv \
13-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_id_stage.sv \
14-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_if_stage.sv \
15-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_wb_stage.sv \
16-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_load_store_unit.sv \
17-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_multdiv_slow.sv \
18-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_multdiv_fast.sv \
19-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_prefetch_buffer.sv \
20-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_fetch_fifo.sv \
21-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_pmp.sv \
22-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_csr.sv \
23-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_core.sv \
24-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_register_file_ff.sv \
5+
export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.sv)) \
256
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/syn/rtl/prim_clock_gating.v
267

278
export VERILOG_INCLUDE_DIRS = \

‎flow/designs/sky130hd/ibex/config.mk‎

Lines changed: 1 addition & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -2,26 +2,7 @@ export DESIGN_NICKNAME = ibex
22
export DESIGN_NAME = ibex_core
33
export PLATFORM = sky130hd
44

5-
export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_pkg.sv \
6-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_alu.sv \
7-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_compressed_decoder.sv \
8-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_controller.sv \
9-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_cs_registers.sv \
10-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_counter.sv \
11-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_decoder.sv \
12-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_ex_block.sv \
13-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_id_stage.sv \
14-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_if_stage.sv \
15-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_wb_stage.sv \
16-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_load_store_unit.sv \
17-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_multdiv_slow.sv \
18-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_multdiv_fast.sv \
19-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_prefetch_buffer.sv \
20-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_fetch_fifo.sv \
21-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_pmp.sv \
22-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_csr.sv \
23-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_core.sv \
24-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_register_file_ff.sv \
5+
export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.sv)) \
256
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/syn/rtl/prim_clock_gating.v
267

278
export VERILOG_INCLUDE_DIRS = \

‎flow/designs/sky130hs/ibex/config.mk‎

Lines changed: 1 addition & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -2,26 +2,7 @@ export DESIGN_NICKNAME = ibex
22
export DESIGN_NAME = ibex_core
33
export PLATFORM = sky130hs
44

5-
export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_pkg.sv \
6-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_alu.sv \
7-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_compressed_decoder.sv \
8-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_controller.sv \
9-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_cs_registers.sv \
10-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_counter.sv \
11-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_decoder.sv \
12-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_ex_block.sv \
13-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_id_stage.sv \
14-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_if_stage.sv \
15-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_wb_stage.sv \
16-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_load_store_unit.sv \
17-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_multdiv_slow.sv \
18-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_multdiv_fast.sv \
19-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_prefetch_buffer.sv \
20-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_fetch_fifo.sv \
21-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_pmp.sv \
22-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_csr.sv \
23-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_core.sv \
24-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_register_file_ff.sv \
5+
export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.sv)) \
256
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/syn/rtl/prim_clock_gating.v
267

278
export VERILOG_INCLUDE_DIRS = \

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