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Merge pull request #2919 from The-OpenROAD-Project-staging/gf12-bp-quad-dual
updated configs for gf12 bp_dual & bp_quad
2 parents af4b4a9 + e8eb31a commit 88a6db4

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4 files changed

+162
-10
lines changed

4 files changed

+162
-10
lines changed

‎flow/designs/gf12/bp_dual/config.mk‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -15,9 +15,9 @@ export RTLMP_FENCE_LY ?= 700
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export RTLMP_FENCE_UX ?= 2450
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export RTLMP_FENCE_UY ?= 2300
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18+
export SYNTH_NETLIST_FILES = $(PLATFORM_DIR)/bp/bsg_ac_black_parrot_dual_core_v0/yosys/bp_dual_hier_yosys_netlist.v
1819
export VERILOG_FILES = $(PLATFORM_DIR)/bp/bsg_ac_black_parrot_dual_core_v0/bsg_chip.sv2v.v \
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$(PLATFORM_DIR)/bp/IN12LP_GPIO18_13M9S30P.blackbox.v
20-
export SYNTH_NETLIST_FILES = $(PLATFORM_DIR)/bp/bsg_ac_black_parrot_dual_core_v0/yosys/bp_dual_hier_yosys_netlist.v
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export SDC_FILE = $(PLATFORM_DIR)/bp/bsg_ac_black_parrot_dual_core_v0/bsg_chip.elab.v.sdc
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‎flow/designs/gf12/bp_dual/rules-base.json‎

Lines changed: 66 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,66 @@
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{
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"constraints__clocks__count": {
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"value": 8,
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"compare": "=="
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},
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"placeopt__design__instance__area": {
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"value": 959122,
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"compare": "<="
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},
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"placeopt__design__instance__count__stdcell": {
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"value": 975165,
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"compare": "<="
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},
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"detailedplace__design__violations": {
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"value": 0,
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"compare": "=="
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},
18+
"cts__design__instance__count__setup_buffer": {
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"value": 84797,
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"compare": "<="
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},
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"cts__design__instance__count__hold_buffer": {
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"value": 84797,
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"compare": "<="
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},
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"globalroute__antenna_diodes_count": {
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"value": 0,
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"compare": "<="
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},
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"detailedroute__route__wirelength": {
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"value": 14955489,
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"compare": "<="
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},
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"detailedroute__route__drc_errors": {
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"value": 0,
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"compare": "<="
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},
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"detailedroute__antenna__violating__nets": {
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"value": 0,
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"compare": "<="
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},
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"detailedroute__antenna_diodes_count": {
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"value": 5,
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"compare": "<="
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},
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"finish__timing__setup__ws": {
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"value": -280.69,
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"compare": ">="
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},
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"finish__design__instance__area": {
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"value": 977391,
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"compare": "<="
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},
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"finish__timing__drv__setup_violation_count": {
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"value": 42398,
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"compare": "<="
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},
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"finish__timing__drv__hold_violation_count": {
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"value": 100,
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"compare": "<="
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},
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"finish__timing__wns_percent_delay": {
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"value": -20.74,
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"compare": ">="
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}
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}

‎flow/designs/gf12/bp_quad/config.mk‎

Lines changed: 29 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -3,13 +3,25 @@ export DESIGN_NAME = bsg_chip
33
export PLATFORM = gf12
44

55
export SYNTH_HIERARCHICAL = 1
6-
export SYNTH_MINIMUM_KEEP_SIZE ?= 1000
6+
#
7+
# RTL_MP Settings
8+
export RTLMP_MAX_INST = 30000
9+
export RTLMP_MIN_INST = 10000
10+
export RTLMP_MAX_MACRO = 24
11+
export RTLMP_MIN_MACRO = 4
12+
#
13+
export RTLMP_FENCE_LX ?= 700
14+
export RTLMP_FENCE_LY ?= 700
15+
export RTLMP_FENCE_UX ?= 2450
16+
export RTLMP_FENCE_UY ?= 2300
717

8-
export SYNTH_NETLIST_FILES = $(PLATFORM_DIR)/bp/bsg_ac_black_parrot_quad_core_v0/bp_quad_block/yosys/bp_quad_yosys_netlist.v
9-
export VERILOG_FILES = $(PLATFORM_DIR)/bp/bsg_ac_black_parrot_quad_core_v0/bp_quad_block/rtl/bsg_chip_block.sv2v.v
18+
export SYNTH_MINIMUM_KEEP_SIZE ?= 1000
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20+
export VERILOG_FILES = $(PLATFORM_DIR)/bp/bsg_ac_black_parrot_quad_core_v0/bsg_chip.sv2v.v \
21+
$(PLATFORM_DIR)/bp/IN12LP_GPIO18_13M9S30P.blackbox.v
22+
export SYNTH_NETLIST_FILES = $(PLATFORM_DIR)/bp/bsg_ac_black_parrot_quad_core_v0/yosys/bp_quad_hier_yosys_netlist.v
1123

12-
export SDC_FILE = $(PLATFORM_DIR)/bp/bsg_ac_black_parrot_quad_core_v0/bp_quad_block/sdc/bsg_chip.sdc
24+
export SDC_FILE = $(PLATFORM_DIR)/bp/bsg_ac_black_parrot_quad_core_v0/bsg_chip.elab.v.sdc
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1426
export WRAP_LEFS = $(PLATFORM_DIR)/lef/gf12_1r1w_d32_w64_m1.lef \
1527
$(PLATFORM_DIR)/lef/gf12_1rw_d128_w116_m2_bit.lef \
@@ -18,13 +30,17 @@ export WRAP_LEFS = $(PLATFORM_DIR)/lef/gf12_1r1w_d32_w64_m1.lef \
1830
$(PLATFORM_DIR)/lef/gf12_1rw_d64_w124_m2_bit.lef \
1931
$(PLATFORM_DIR)/lef/gf12_1rw_d64_w62_m2_bit.lef
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33+
export ADDITIONAL_LEFS = $(PLATFORM_DIR)/lef/IN12LP_GPIO18_13M9S30P.lef \
34+
$(PLATFORM_DIR)/lef/CDMM_13M_3Mx_2Cx_4Kx_2Hx_2Gx_LB.lef
35+
2136
export WRAP_LIBS = $(PLATFORM_DIR)/lib/gf12_1r1w_d32_w64_m1_ffpg_sigcmin_0p88v_0p88v_m40c.lib \
2237
$(PLATFORM_DIR)/lib/gf12_1rw_d128_w116_m2_bit_ffpg_sigcmin_0p88v_0p88v_m40c.lib \
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$(PLATFORM_DIR)/lib/gf12_1rw_d256_w48_m2_ffpg_sigcmin_0p88v_0p88v_m40c.lib \
2439
$(PLATFORM_DIR)/lib/gf12_1rw_d512_w64_m2_byte_ffpg_sigcmin_0p88v_0p88v_m40c.lib \
2540
$(PLATFORM_DIR)/lib/gf12_1rw_d64_w124_m2_bit_ffpg_sigcmin_0p88v_0p88v_m40c.lib \
2641
$(PLATFORM_DIR)/lib/gf12_1rw_d64_w62_m2_bit_ffpg_sigcmin_0p88v_0p88v_m40c.lib
2742

43+
export ADDITIONAL_LIBS = $(PLATFORM_DIR)/lib/IN12LP_GPIO18_13M9S30P_TT_0P8_1P8_25.lib
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2945
export ADDITIONAL_GDS = $(PLATFORM_DIR)/gds/gf12_1r1w_d32_w64_m1.gds2 \
3046
$(PLATFORM_DIR)/gds/gf12_1rw_d128_w116_m2_bit.gds2 \
@@ -37,14 +53,18 @@ export ADDITIONAL_GDS = $(PLATFORM_DIR)/gds/gf12_1r1w_d32_w64_m1.gds2 \
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3854
export SEAL_GDS = $(PLATFORM_DIR)/gds/crackstop_3x3.gds
3955

40-
export DIE_AREA = 0 0 1800 1800
41-
export CORE_AREA = 5 5 1795 1795
42-
export PLACE_PINS_ARGS = -exclude left:* -exclude right:* -exclude top:* -exclude bottom:0-800 -exclude bottom:1200-1800
56+
export FOOTPRINT_TCL = $(PLATFORM_DIR)/bp/footprint.tcl
57+
58+
export DIE_AREA = 0 0 3000 3000
59+
export CORE_AREA = 200 200 2800 2800
60+
61+
export ABC_CLOCK_PERIOD_IN_PS = 1250
4362

44-
export PLACE_DENSITY_LB_ADDON = 0.02
63+
export TNS_END_PERCENT = 0
64+
export PLACE_DENSITY = 0.40
4565

4666
export MACRO_WRAPPERS = $(PLATFORM_DIR)/bp/wrappers/wrappers.tcl
4767

4868
export PDN_TCL = $(PLATFORM_DIR)/cfg/pdn_grid_strategy_13m_9T.top.tcl
4969

50-
export MACRO_PLACE_HALO = 5 5
70+
export MACRO_PLACE_HALO = 7 7

‎flow/designs/gf12/bp_quad/rules-base.json‎

Lines changed: 66 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,66 @@
1+
{
2+
"constraints__clocks__count": {
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"value": 8,
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"compare": "=="
5+
},
6+
"placeopt__design__instance__area": {
7+
"value": 1729278,
8+
"compare": "<="
9+
},
10+
"placeopt__design__instance__count__stdcell": {
11+
"value": 1606228,
12+
"compare": "<="
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},
14+
"detailedplace__design__violations": {
15+
"value": 0,
16+
"compare": "=="
17+
},
18+
"cts__design__instance__count__setup_buffer": {
19+
"value": 139672,
20+
"compare": "<="
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},
22+
"cts__design__instance__count__hold_buffer": {
23+
"value": 139672,
24+
"compare": "<="
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},
26+
"globalroute__antenna_diodes_count": {
27+
"value": 0,
28+
"compare": "<="
29+
},
30+
"detailedroute__route__wirelength": {
31+
"value": 32527768,
32+
"compare": "<="
33+
},
34+
"detailedroute__route__drc_errors": {
35+
"value": 0,
36+
"compare": "<="
37+
},
38+
"detailedroute__antenna__violating__nets": {
39+
"value": 0,
40+
"compare": "<="
41+
},
42+
"detailedroute__antenna_diodes_count": {
43+
"value": 5,
44+
"compare": "<="
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},
46+
"finish__timing__setup__ws": {
47+
"value": -255.36,
48+
"compare": ">="
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},
50+
"finish__design__instance__area": {
51+
"value": 1765388,
52+
"compare": "<="
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},
54+
"finish__timing__drv__setup_violation_count": {
55+
"value": 69836,
56+
"compare": "<="
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},
58+
"finish__timing__drv__hold_violation_count": {
59+
"value": 109,
60+
"compare": "<="
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},
62+
"finish__timing__wns_percent_delay": {
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"value": -16.47,
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"compare": ">="
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}
66+
}

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