Merge pull request #2804 from The-OpenROAD-Project-staging/port-ibex-jpeg-intel16

Ported ibex and jpeg from intel22 to intel16

Author: maliberty

flow/designs/intel22/ibex/config.mk flow/designs/intel16/ibex/config.mkflow/designs/intel22/ibex/config.mk renamed to flow/designs/intel16/ibex/config.mk

@@ -3,7 +3,7 @@ DESIGN_PDK_HOME              := $(realpath $(shell dirname $(realpath $(lastword
 
 export DESIGN_NICKNAME = ibex
 export DESIGN_NAME = ibex_core
-export PLATFORM    = intel22
+export PLATFORM    = intel16
 
 export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.v))
 export SDC_FILE      = $(DESIGN_DIR)/constraint.sdc

flow/designs/intel22/ibex/constraint.sdc flow/designs/intel16/ibex/constraint.sdcflow/designs/intel22/ibex/constraint.sdc renamed to flow/designs/intel16/ibex/constraint.sdc

@@ -1,58 +1,70 @@
 {
     "synth__design__instance__area__stdcell": {
-        "value": 41593.54,
+        "value": 9265.72,
         "compare": "<="
     },
     "constraints__clocks__count": {
         "value": 1,
         "compare": "=="
     },
     "placeopt__design__instance__area": {
-        "value": 67233,
+        "value": 13342,
         "compare": "<="
     },
     "placeopt__design__instance__count__stdcell": {
-        "value": 78381,
+        "value": 17697,
         "compare": "<="
     },
     "detailedplace__design__violations": {
         "value": 0,
         "compare": "=="
     },
     "cts__design__instance__count__setup_buffer": {
-        "value": 6816,
+        "value": 1539,
         "compare": "<="
     },
     "cts__design__instance__count__hold_buffer": {
-        "value": 6816,
+        "value": 1539,
+        "compare": "<="
+    },
+    "globalroute__antenna_diodes_count": {
+        "value": 0,
         "compare": "<="
     },
     "detailedroute__route__wirelength": {
-        "value": 881231,
+        "value": 290303,
         "compare": "<="
     },
     "detailedroute__route__drc_errors": {
-        "value": 1,
+        "value": 0,
+        "compare": "<="
+    },
+    "detailedroute__antenna__violating__nets": {
+        "value": 0,
+        "compare": "<="
+    },
+    "detailedroute__antenna_diodes_count": {
+        "value": 5,
         "compare": "<="
     },
     "finish__timing__setup__ws": {
-        "value": 0.0,
+        "value": -1440.76,
         "compare": ">="
     },
     "finish__design__instance__area": {
-        "value": 67387,
+        "value": 14676,
         "compare": "<="
     },
     "finish__timing__drv__setup_violation_count": {
-        "value": 3408,
+        "value": 1584,
         "compare": "<="
     },
     "finish__timing__drv__hold_violation_count": {
         "value": 100,
         "compare": "<="
     },
     "finish__timing__wns_percent_delay": {
-        "value": -10.0,
+        "value": -50.01,
         "compare": ">="
     }
 }

flow/designs/intel16/ibex/metadata-base-ok.json

@@ -3,13 +3,13 @@ DESIGN_PDK_HOME              := $(realpath $(shell dirname $(realpath $(lastword
 
 export DESIGN_NICKNAME = jpeg
 export DESIGN_NAME = jpeg_encoder
-export PLATFORM    = intel22
+export PLATFORM    = intel16
 
 export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.v))
 export VERILOG_INCLUDE_DIRS = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/include
 export SDC_FILE      = $(DESIGN_DIR)/constraint.sdc
 
-export CORE_UTILIZATION = 30
+export CORE_UTILIZATION = 20
 export CORE_ASPECT_RATIO = 1
 export CORE_MARGIN = 2