Merge pull request #3551 from The-OpenROAD-Project-staging/secure-reorder-alu

Added ALU module reordering feature for synthesis

Author: maliberty

docs/user/FlowVariables.md

@@ -241,6 +241,8 @@ configuration file.
 | <a name="SYNTH_NETLIST_FILES"></a>SYNTH_NETLIST_FILES| Skips synthesis and uses the supplied netlist files. If the netlist files contains duplicate modules, which can happen when using hierarchical synthesis on indvidual netlist files and combining here, subsequent modules are silently ignored and only the first module is used.| |
 | <a name="SYNTH_OPT_HIER"></a>SYNTH_OPT_HIER| Optimize constants across hierarchical boundaries.| |
 | <a name="SYNTH_RETIME_MODULES"></a>SYNTH_RETIME_MODULES| *This is an experimental option and may cause adverse effects.* *No effort has been made to check if the retimed RTL is logically equivalent to the non-retimed RTL.* List of modules to apply automatic retiming to. These modules must not get dissolved and as such they should either be the top module or be included in SYNTH_KEEP_MODULES. The main use case is to quickly identify if performance can be improved by manually retiming the input RTL. Retiming will treat module ports like register endpoints/startpoints. The objective function of retiming isn't informed by SDC, even the clock period is ignored. As such, retiming will optimize for best delay at potentially high register number cost. Automatic retiming can produce suboptimal results as its timing model is crude and it doesn't find the optimal distribution of registers on long pipelines. See OR discussion #8080.| |
+| <a name="SYNTH_WRAPPED_ADDERS"></a>SYNTH_WRAPPED_ADDERS| Specify the adder modules that can be used for synthesis, separated by commas. The default adder module is determined by the first element of this variable.| |
+| <a name="SYNTH_WRAPPED_MULTIPLIERS"></a>SYNTH_WRAPPED_MULTIPLIERS| Specify the multiplier modules that can be used for synthesis, separated by commas. The default multiplier module is determined by the first element of this variable.| |
 | <a name="SYNTH_WRAPPED_OPERATORS"></a>SYNTH_WRAPPED_OPERATORS| Synthesize multiple architectural options for each arithmetic operator in the design. These options are available for switching among in later stages of the flow.| |
 | <a name="TAPCELL_TCL"></a>TAPCELL_TCL| Path to Endcap and Welltie cells file.| |
 | <a name="TAP_CELL_NAME"></a>TAP_CELL_NAME| Name of the cell to use in tap cell insertion.| |
@@ -278,6 +280,8 @@ configuration file.
 - [SYNTH_NETLIST_FILES](#SYNTH_NETLIST_FILES)
 - [SYNTH_OPT_HIER](#SYNTH_OPT_HIER)
 - [SYNTH_RETIME_MODULES](#SYNTH_RETIME_MODULES)
+- [SYNTH_WRAPPED_ADDERS](#SYNTH_WRAPPED_ADDERS)
+- [SYNTH_WRAPPED_MULTIPLIERS](#SYNTH_WRAPPED_MULTIPLIERS)
 - [TIEHI_CELL_AND_PORT](#TIEHI_CELL_AND_PORT)
 - [TIELO_CELL_AND_PORT](#TIELO_CELL_AND_PORT)
 - [VERILOG_DEFINES](#VERILOG_DEFINES)

flow/scripts/synth_wrap_operators.tcl

@@ -1,3 +1,4 @@
+# Set arithmetic operator modules. Default is the first module in the list.
 set deferred_cells {
   {
     \$alu
@@ -15,6 +16,40 @@ set deferred_cells {
   }
 }
 
+# Reorder the modules based on envar
+proc reorder_deferred_cells { deferred_cells_var index env_var } {
+  upvar $deferred_cells_var deferred_cells
+
+  if { ![info exists ::env($env_var)] } {
+    return
+  }
+
+  set cell_def [lindex $deferred_cells $index]
+
+  # Build lookup dict
+  set choice_map {}
+  foreach choice [lrange $cell_def 2 end] {
+    dict set choice_map [lindex $choice 0] $choice
+  }
+
+  # Build new choices
+  set new_choices {}
+  foreach name [split $::env($env_var) ","] {
+    if { [dict exists $choice_map $name] } {
+      lappend new_choices [dict get $choice_map $name]
+    } else {
+      puts "Warning: Unknown choice '$name' ignored for $env_var"
+    }
+  }
+
+  # Replace cell
+  lset deferred_cells $index [linsert $new_choices 0 {*}[lrange $cell_def 0 1]]
+}
+
+# Apply custom orders
+reorder_deferred_cells deferred_cells 0 SYNTH_WRAPPED_ADDERS
+reorder_deferred_cells deferred_cells 1 SYNTH_WRAPPED_MULTIPLIERS
+
 techmap {*}[join [lmap cell $deferred_cells { string cat "-dont_map [lindex $cell 0]" }] " "]
 
 foreach info $deferred_cells {

flow/scripts/variables.yaml

@@ -299,6 +299,18 @@ SYNTH_WRAPPED_OPERATORS:
     the flow.
   stages:
     - All stages
+SYNTH_WRAPPED_ADDERS:
+  description: >
+    Specify the adder modules that can be used for synthesis, separated by commas.
+    The default adder module is determined by the first element of this variable.
+  stages:
+    - synth
+SYNTH_WRAPPED_MULTIPLIERS:
+  description: >
+    Specify the multiplier modules that can be used for synthesis, separated by commas.
+    The default multiplier module is determined by the first element of this variable.
+  stages:
+    - synth
 SWAP_ARITH_OPERATORS:
   description: >
     Improve timing QoR by swapping ALU and MULT arithmetic operators.