docs: Update for yosys-slang

Signed-off-by: Martin Povišer <[email protected]>

Author: povik

docs/tutorials/FlowTutorial.md

@@ -187,11 +187,11 @@ minimum required timing constraint.
 create_clock -name core_clock -period 17.4 [get_ports {clk_i}]
 ```
 
-### Design Input Verilog
+### Design Input SystemVerilog
 
-The Verilog input files are located in `./designs/src/ibex/`
+The SystemVerilog input files are located in `./designs/src/ibex/`
 
-The design is defined in `ibex_core.v` available
+The design is defined in `ibex_core.sv` available
 [here](https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/blob/master/flow/designs/src/ibex/ibex_core.v).
 
 Refer to the `ibex` design `README.md`

docs/user/BuildLocally.md

@@ -32,6 +32,7 @@ up the environment. The `make` command runs from RTL-GDSII generation for defaul
 ``` shell
 source ./env.sh
 yosys -help
+yosys -m slang -p "slang_version"
 openroad -help
 cd flow
 make

docs/user/BuildWithDocker.md

@@ -79,6 +79,7 @@ Then, inside docker:
 ``` shell
 source ./env.sh
 yosys -help
+yosys -m slang -p "slang_version"
 openroad -help
 cd flow
 make

docs/user/BuildWithPrebuilt.md

@@ -63,6 +63,7 @@ export YOSYS_EXE=$(command -v yosys)
 export LD_LIBRARY_PATH="<klayout_location>/bin:$PATH"
 
 yosys -help
+yosys -m slang -p "slang_version"
 openroad -help
 cd flow
 make