@@ -42,10 +42,10 @@ export RC_FILE = $(PLATFORM_DIR)/setRC.tcl
4242
4343# set the TIEHI/TIELO cells
4444export TIEHI_CELL_AND_PORT = gf180mcu_fd_sc_mcu$(TRACK_OPTION )$(POWER_OPTION ) __tieh Z
45- export TIELO_CELL_AND_PORT = gf180mcu_fd_sc_mcu$(TRACK_OPTION )$(POWER_OPTION ) __tiel Z
45+ export TIELO_CELL_AND_PORT = gf180mcu_fd_sc_mcu$(TRACK_OPTION )$(POWER_OPTION ) __tiel ZN
4646
4747# Set yosys-abc clock period to first "clk_period" value or "-period" value found in sdc file
48- export ABC_CLOCK_PERIOD_IN_PS ?= $(shell sed -nr "s/^set\s+clk_period\s+(\S+) .*|.*-period\s+(\S+).*/\1\2/p" $(SDC_FILE ) | head -1 | awk '{print $$1}')
48+ export ABC_CLOCK_PERIOD_IN_PS ?= $(shell sed -nr "s/^set\s+clk_period\s+(\S+) .*|.*-period\s+(\S+).*/\1\2/p" $(SDC_FILE ) | head -1 | awk '{print $$1*1000 }')
4949export ABC_DRIVER_CELL = gf180mcu_fd_sc_mcu$(TRACK_OPTION )$(POWER_OPTION ) __buf_4
5050export ABC_LOAD_IN_FF = 0.01343
5151
6565export PLACE_SITE = GF018hv5v_mcu_sc7
6666endif
6767
68- # IO Pin fix margin
69- export IO_PIN_MARGIN ?= 25
70-
7168# IO Placer pin layers
7269export IO_PLACER_H ?= Metal3
7370export IO_PLACER_V ?= Metal4
@@ -89,21 +86,9 @@ export MACRO_PLACE_CHANNEL ?= 20.16 20.16
8986export CELL_PAD_IN_SITES_GLOBAL_PLACEMENT ?= 2
9087export CELL_PAD_IN_SITES_DETAIL_PLACEMENT ?= 1
9188
92- # resizer repair_long_wires -max_length
93- export MAX_WIRE_LENGTH = 150
94-
9589# global placement density
9690export PLACE_DENSITY ?= 0.40
9791
98- # adjustment parameter for placer and global router's routability-driven loop
99- #
100- # if routing resources are highly reduced in global router (e.g. higher value in below)
101- # placer will bloat lots of cells in each RD iteration and cause unstableness.
102- #
103- # will be used in script/global_place.tcl
104- export REPLACE_FASTROUTE_RESOURCE_ADJ_23 = 0.7
105- export REPLACE_FASTROUTE_RESOURCE_ADJ_OTHER = 0.4
106-
10792# --------------------------------------------------------
10893# CTS
10994# --------------------------------------------------------
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