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jeffng-orjeffng-or
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Enabled cva6 on asap7 using yosys-slang
updated RTL files list and clock period Signed-off-by: Jeff Ng <[email protected]>
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‎flow/designs/asap7/cva6/config.mk‎

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#
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# TODO before enablement: pipe VERILOG_DEFINES through to yosys
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#
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export PLATFORM = asap7
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export DESIGN_NAME = cva6
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export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cvfpu/src/fpnew_pkg.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/include/config_pkg.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/include/cv32a65x_config_pkg.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/include/riscv_pkg.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/include/ariane_pkg.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/vendor/pulp-platform/axi/src/axi_pkg.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/include/wt_cache_pkg.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/include/std_cache_pkg.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/include/build_config_pkg.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cvxif_example/include/cvxif_instr_pkg.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/vendor/pulp-platform/common_cells/src/cf_math_pkg.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/hpdcache/rtl/src/hwpf_stride/hwpf_stride_pkg.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_pkg.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cvfpu/src/fpnew_cast_multi.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cvfpu/src/fpnew_classifier.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cvfpu/src/fpnew_divsqrt_multi.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cvfpu/src/fpnew_fma_multi.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cvfpu/src/fpnew_fma.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cvfpu/src/fpnew_noncomp.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cvfpu/src/fpnew_opgroup_block.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cvfpu/src/fpnew_opgroup_fmt_slice.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cvfpu/src/fpnew_opgroup_multifmt_slice.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cvfpu/src/fpnew_rounding.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cvfpu/src/fpnew_top.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/defs_div_sqrt_mvp.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/control_mvp.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/div_sqrt_top_mvp.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/iteration_div_sqrt_mvp.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/norm_div_sqrt_mvp.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/nrbd_nrsc_mvp.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/preprocess_mvp.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cvxif_compressed_if_driver.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cvxif_issue_register_commit_if_driver.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cvxif_fu.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cvxif_example/instr_decoder.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cvxif_example/compressed_instr_decoder.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cvxif_example/copro_alu.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/vendor/pulp-platform/common_cells/src/fifo_v3.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/vendor/pulp-platform/common_cells/src/lfsr.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/vendor/pulp-platform/common_cells/src/lfsr_8bit.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/vendor/pulp-platform/common_cells/src/stream_arbiter.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/vendor/pulp-platform/common_cells/src/stream_arbiter_flushable.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/vendor/pulp-platform/common_cells/src/stream_mux.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/vendor/pulp-platform/common_cells/src/stream_demux.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/vendor/pulp-platform/common_cells/src/lzc.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/vendor/pulp-platform/common_cells/src/rr_arb_tree.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/vendor/pulp-platform/common_cells/src/shift_reg.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/vendor/pulp-platform/common_cells/src/unread.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/vendor/pulp-platform/common_cells/src/popcount.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/vendor/pulp-platform/common_cells/src/exp_backoff.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/vendor/pulp-platform/common_cells/src/counter.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/vendor/pulp-platform/common_cells/src/delta_counter.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cva6.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cva6_rvfi_probes.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/alu.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/fpu_wrap.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/branch_unit.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/compressed_decoder.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/macro_decoder.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/controller.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/zcmt_decoder.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/csr_buffer.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/csr_regfile.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/decoder.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/ex_stage.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/instr_realign.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/id_stage.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/issue_read_operands.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/issue_stage.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/load_unit.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/load_store_unit.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/lsu_bypass.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/mult.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/multiplier.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/serdiv.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/perf_counters.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/ariane_regfile_ff.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/scoreboard.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/store_buffer.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/amo_buffer.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/store_unit.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/commit_stage.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/axi_shim.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cva6_accel_first_pass_decoder_stub.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/acc_dispatcher.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cva6_fifo_v3.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/frontend/btb.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/frontend/bht.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/frontend/bht2lvl.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/frontend/ras.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/frontend/instr_scan.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/frontend/instr_queue.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/frontend/frontend.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/wt_dcache_ctrl.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/wt_dcache_mem.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/wt_dcache_missunit.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/wt_dcache_wbuffer.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/wt_dcache.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/cva6_icache.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/wt_cache_subsystem.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/wt_axi_adapter.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/tag_cmp.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/axi_adapter.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/cache_ctrl.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/cva6_icache_axi_wrapper.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/std_cache_subsystem.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/std_nbdcache.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/hpdcache/rtl/src/utils/hpdcache_mem_resp_demux.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/hpdcache/rtl/src/utils/hpdcache_mem_to_axi_read.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/hpdcache/rtl/src/utils/hpdcache_mem_to_axi_write.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/cva6_hpdcache_subsystem.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/cva6_hpdcache_subsystem_axi_arbiter.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/cva6_hpdcache_if_adapter.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/cva6_hpdcache_wrapper.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/hpdcache/rtl/src/common/macros/blackbox/hpdcache_sram_1rw.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/hpdcache/rtl/src/common/macros/blackbox/hpdcache_sram_wbyteenable_1rw.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/hpdcache/rtl/src/common/macros/blackbox/hpdcache_sram_wmask_1rw.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/pmp/src/pmp.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/pmp/src/pmp_entry.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/pmp/src/pmp_data_if.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/common/local/util/tc_sram_wrapper.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/common/local/util/tc_sram_wrapper_cache_techno.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/vendor/pulp-platform/tech_cells_generic/src/rtl/tc_sram.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/common/local/util/sram.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/common/local/util/sram_cache.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cva6_mmu/cva6_mmu.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cva6_mmu/cva6_ptw.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cva6_mmu/cva6_tlb.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cva6_mmu/cva6_shared_tlb.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/hpdcache/rtl/src/utils/hpdcache_mem_req_read_arbiter.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/hpdcache/rtl/src/utils/hpdcache_mem_req_write_arbiter.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_demux.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_lfsr.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_sync_buffer.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_fifo_reg.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_fxarb.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_rrarb.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_mux.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_decoder.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_1hot_to_binary.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_prio_1hot_encoder.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_sram.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_sram_wbyteenable.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_sram_wmask.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_regbank_wbyteenable_1rw.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_regbank_wmask_1rw.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_data_downsize.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_data_upsize.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_data_resize.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/hpdcache/rtl/src/hwpf_stride/hwpf_stride.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/hpdcache/rtl/src/hwpf_stride/hwpf_stride_arb.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/hpdcache/rtl/src/hwpf_stride/hwpf_stride_wrapper.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_amo.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_cmo.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_core_arbiter.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_ctrl.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_ctrl_pe.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_memctrl.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_miss_handler.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_mshr.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_rtab.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_uncached.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_victim_plru.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_victim_random.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_victim_sel.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_wbuf.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/hpdcache/rtl/src/hpdcache_flush.sv
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export VERILOG_INCLUDE_DIRS = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/include \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cvfpu/src/common_cells/include \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/hpdcache/rtl/include
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VERILOG_DEFINES += -D HPDCACHE_ASSERT_OFF
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export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc
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export DIE_AREA = 0 0 200 200
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export CORE_AREA = 1.08 1.08 190 190
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export PLACE_DENSITY = 0.40
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# a smoketest for this option, there are a
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# few last gasp iterations
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export SKIP_LAST_GASP ?= 1
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export SYNTH_USE_SLANG = 1

‎flow/designs/asap7/cva6/constraint.sdc‎

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# Derived from cva6_synth.tcl and Makefiles
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set clk_name main_clk
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set clk_port clk_i
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set clk_ports_list [list $clk_port]
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set clk_period 1300
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set input_delay 0.46
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set output_delay 0.11
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create_clock [get_ports $clk_port] -name $clk_name -period $clk_period
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# #set_dont_touch to keep sram as black boxes
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# set_dont_touch i_cache_subsystem/i_wt_dcache/i_wt_dcache_mem/gen_tag_srams[*].i_tag_sram
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# set_dont_touch i_cache_subsystem/i_wt_dcache/i_wt_dcache_mem/gen_data_banks[*].i_data_sram
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# set_dont_touch i_cache_subsystem/i_cva6_icache/gen_sram[*].data_sram
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# set_dont_touch i_cache_subsystem/i_cva6_icache/gen_sram[*].tag_sram
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# #constraint the timing to and from the sram black boxes
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# set_input_delay -clock main_clk -max $input_delay i_cache_subsystem/i_wt_dcache/i_wt_dcache_mem/gen_tag_srams_*__i_tag_sram/gen_cut_*__gen_mem_i_tc_sram_wrapper/rdata_o[*]
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# set_input_delay -clock main_clk -max $input_delay i_cache_subsystem/i_wt_dcache/i_wt_dcache_mem/gen_data_banks_*__i_data_sram/gen_cut_*__gen_mem_i_tc_sram_wrapper/rdata_o[*]
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# set_input_delay -clock main_clk -max $input_delay i_cache_subsystem/i_cva6_icache/gen_sram_*__data_sram/gen_cut_*__gen_mem_i_tc_sram_wrapper/rdata_o[*]
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# set_input_delay -clock main_clk -max $input_delay i_cache_subsystem/i_cva6_icache/gen_sram_*__tag_sram/gen_cut_*__gen_mem_i_tc_sram_wrapper/rdata_o[*]
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# set_output_delay $output_delay -max -clock main_clk i_cache_subsystem/i_wt_dcache/i_wt_dcache_mem/gen_tag_srams_*__i_tag_sram/gen_cut_*__gen_mem_i_tc_sram_wrapper/addr_i[*]
23+
# set_output_delay $output_delay -max -clock main_clk i_cache_subsystem/i_wt_dcache/i_wt_dcache_mem/gen_data_banks_*__i_data_sram/gen_cut_*__gen_mem_i_tc_sram_wrapper/addr_i[*]
24+
# set_output_delay $output_delay -max -clock main_clk i_cache_subsystem/i_cva6_icache/gen_sram_*__data_sram/gen_cut_*__gen_mem_i_tc_sram_wrapper/addr_i[*]
25+
# set_output_delay $output_delay -max -clock main_clk i_cache_subsystem/i_cva6_icache/gen_sram_*__tag_sram/gen_cut_*__gen_mem_i_tc_sram_wrapper/addr_i[*]
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set_false_path -to [get_ports {rvfi_probes_o}]

‎flow/designs/asap7/cva6/rules-base.json‎

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{
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"synth__design__instance__area__stdcell": {
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"value": 13337.62,
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"compare": "<="
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},
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"constraints__clocks__count": {
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"value": 1,
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"compare": "=="
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},
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"placeopt__design__instance__area": {
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"value": 15798,
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"compare": "<="
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},
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"placeopt__design__instance__count__stdcell": {
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"value": 130789,
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"compare": "<="
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},
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"detailedplace__design__violations": {
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"value": 0,
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"compare": "=="
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},
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"cts__design__instance__count__setup_buffer": {
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"value": 11373,
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"compare": "<="
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},
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"cts__design__instance__count__hold_buffer": {
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"value": 11373,
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"compare": "<="
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},
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"globalroute__antenna_diodes_count": {
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"value": 0,
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"compare": "<="
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},
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"detailedroute__route__wirelength": {
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"value": 1241141,
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"compare": "<="
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},
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"detailedroute__route__drc_errors": {
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"value": 0,
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"compare": "<="
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},
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"detailedroute__antenna__violating__nets": {
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"value": 0,
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"compare": "<="
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},
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"detailedroute__antenna_diodes_count": {
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"value": 5,
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"compare": "<="
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},
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"finish__timing__setup__ws": {
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"value": -181.59,
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"compare": ">="
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},
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"finish__design__instance__area": {
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"value": 16112,
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"compare": "<="
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},
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"finish__timing__drv__setup_violation_count": {
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"value": 5686,
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"compare": "<="
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},
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"finish__timing__drv__hold_violation_count": {
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"value": 100,
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"compare": "<="
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},
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"finish__timing__wns_percent_delay": {
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"value": -18.66,
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"compare": ">="
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}
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}

‎flow/designs/src/cva6/README.md‎

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Extracted from https://github.com/openhwgroup/cva6

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