Merge remote-tracking branch 'private/master' into secure-gpl-binSize-float

Author: gudeh

docs/user/FlowVariables.md

@@ -196,7 +196,7 @@ configuration file.
 | <a name="VERILOG_FILES"></a>VERILOG_FILES| The path to the design Verilog files or JSON files providing a description of modules (check `yosys -h write_json` for more details).| | |
 | <a name="VERILOG_INCLUDE_DIRS"></a>VERILOG_INCLUDE_DIRS| Specifies the include directories for the Verilog input files.| | |
 | <a name="VERILOG_TOP_PARAMS"></a>VERILOG_TOP_PARAMS| Apply toplevel params (if exist).| | |
-| <a name="YOSYS_FLAGS"></a>YOSYS_FLAGS| Additional flags to pass to yosys.| | |
+| <a name="YOSYS_FLAGS"></a>YOSYS_FLAGS| Flags to pass to yosys.| -v 3| |
 ## synth variables
 
 - [ABC_AREA](#ABC_AREA)

flow/Makefile

@@ -180,10 +180,6 @@ include $(PLATFORM_DIR)/config.mk
 # is no way to escape space in defaults.py and get "foreach" to work.
 $(foreach line,$(shell $(SCRIPTS_DIR)/defaults.py),$(eval export $(subst __SPACE__, ,$(line))))
 
-# Not normally adjusted by user
-export SYNTH_OPERATIONS_ARGS ?= -extra-map $(FLOW_HOME)/platforms/common/lcu_kogge_stone.v
-export SYNTH_FULL_ARGS ?= $(SYNTH_ARGS) $(SYNTH_OPERATIONS_ARGS)
-
 export DESIGN_CONFIG
 export DESIGN_DIR  = $(dir $(DESIGN_CONFIG))
 export LOG_DIR     = $(WORK_HOME)/logs/$(PLATFORM)/$(DESIGN_NICKNAME)/$(FLOW_VARIANT)
@@ -211,8 +207,6 @@ ifeq (,$(strip $(NUM_CORES)))
 endif
 export NUM_CORES
 
-YOSYS_FLAGS += -v 3
-
 #-------------------------------------------------------------------------------
 # setup all commands used within this flow
 export TIME_BIN   ?= env time

flow/designs/asap7/aes-block/rules-base.json

@@ -24,7 +24,7 @@
         "compare": "<="
     },
     "cts__design__instance__count__hold_buffer": {
-        "value": 1025,
+        "value": 1024,
         "compare": "<="
     },
     "globalroute__antenna_diodes_count": {
@@ -48,23 +48,23 @@
         "compare": "<="
     },
     "finish__timing__setup__ws": {
-        "value": -115.61,
+        "value": -86.3,
         "compare": ">="
     },
     "finish__design__instance__area": {
-        "value": 7354,
+        "value": 7348,
         "compare": "<="
     },
     "finish__timing__drv__setup_violation_count": {
         "value": 478,
         "compare": "<="
     },
     "finish__timing__drv__hold_violation_count": {
-        "value": 326,
+        "value": 319,
         "compare": "<="
     },
     "finish__timing__wns_percent_delay": {
-        "value": -21.47,
+        "value": -21.42,
         "compare": ">="
     }
 }

flow/designs/asap7/aes/rules-base.json

@@ -48,7 +48,7 @@
         "compare": "<="
     },
     "finish__timing__setup__ws": {
-        "value": -85.3,
+        "value": -70.11,
         "compare": ">="
     },
     "finish__design__instance__area": {

flow/designs/asap7/aes_lvt/rules-base.json

@@ -44,11 +44,11 @@
         "compare": "<="
     },
     "detailedroute__antenna_diodes_count": {
-        "value": 0,
+        "value": 5,
         "compare": "<="
     },
     "finish__timing__setup__ws": {
-        "value": -31.87,
+        "value": -29.62,
         "compare": ">="
     },
     "finish__design__instance__area": {
@@ -64,7 +64,7 @@
         "compare": "<="
     },
     "finish__timing__wns_percent_delay": {
-        "value": -13.0,
+        "value": -12.43,
         "compare": ">="
     }
 }

flow/designs/asap7/cva6/config.mk

@@ -126,8 +126,8 @@ export VERILOG_FILES          = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cvfpu
 	$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/pmp/src/pmp.sv \
 	$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/pmp/src/pmp_entry.sv \
 	$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/pmp/src/pmp_data_if.sv \
+	$(PLATFORM_DIR)/verilog/fakeram7_256x32.sv \
 	$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/common/local/util/tc_sram_wrapper.sv \
-	$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/common/local/util/tc_sram_wrapper_cache_techno.sv \
 	$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/vendor/pulp-platform/tech_cells_generic/src/rtl/tc_sram.sv \
 	$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/common/local/util/sram.sv \
 	$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/common/local/util/sram_cache.sv \
@@ -181,6 +181,10 @@ export VERILOG_INCLUDE_DIRS = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/include
 
 VERILOG_DEFINES += -D HPDCACHE_ASSERT_OFF
 
+export ADDITIONAL_LEFS = $(PLATFORM_DIR)/lef/fakeram7_256x32.lef
+
+export ADDITIONAL_LIBS = $(PLATFORM_DIR)/lib/NLDM/fakeram7_256x32.lib
+
 export SDC_FILE               = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc
 
 export DIE_AREA               = 0 0 200 200

flow/designs/asap7/ethmac/rules-base.json

@@ -48,7 +48,7 @@
         "compare": "<="
     },
     "finish__timing__setup__ws": {
-        "value": -200.49,
+        "value": -187.76,
         "compare": ">="
     },
     "finish__design__instance__area": {

flow/designs/asap7/ethmac_lvt/rules-base.json

@@ -48,7 +48,7 @@
         "compare": "<="
     },
     "finish__timing__setup__ws": {
-        "value": -114.81,
+        "value": -90.17,
         "compare": ">="
     },
     "finish__design__instance__area": {

flow/designs/asap7/gcd-ccs/rules-base.json

@@ -52,11 +52,11 @@
         "compare": ">="
     },
     "finish__design__instance__area": {
-        "value": 58,
+        "value": 57,
         "compare": "<="
     },
     "finish__timing__drv__setup_violation_count": {
-        "value": 38,
+        "value": 43,
         "compare": "<="
     },
     "finish__timing__drv__hold_violation_count": {

flow/designs/asap7/gcd/rules-base.json

@@ -32,7 +32,7 @@
         "compare": "<="
     },
     "detailedroute__route__wirelength": {
-        "value": 1423,
+        "value": 1410,
         "compare": "<="
     },
     "detailedroute__route__drc_errors": {
@@ -52,11 +52,11 @@
         "compare": ">="
     },
     "finish__design__instance__area": {
-        "value": 62,
+        "value": 60,
         "compare": "<="
     },
     "finish__timing__drv__setup_violation_count": {
-        "value": 27,
+        "value": 24,
         "compare": "<="
     },
     "finish__timing__drv__hold_violation_count": {